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Searched refs:mdiv (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/clk/exynos/
H A Dclk-pll.c22 unsigned long mdiv, sdiv, pdiv; in pll145x_get_rate() local
25 mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; in pll145x_get_rate()
29 fvco *= mdiv; in pll145x_get_rate()
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c48 u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; in cm_basic_init() local
58 mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & in cm_basic_init()
62 mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; in cm_basic_init()
63 hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - in cm_basic_init()
80 mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & in cm_basic_init()
84 mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; in cm_basic_init()
85 hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - in cm_basic_init()
175 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
197 mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; in cm_get_main_vco_clk_hz()
200 vco = vco * (CLKMGR_MDIV_CONST + mdiv); in cm_get_main_vco_clk_hz()
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/openbmc/u-boot/board/synopsys/iot_devkit/
H A Dconfig.mk1 PLATFORM_CPPFLAGS += -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel…
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos4_setup.h340 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
341 | (mdiv << 16) \
H A Dexynos5_setup.h22 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) argument
/openbmc/u-boot/board/samsung/trats/
H A Dsetup.h229 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
230 | (mdiv << 16) \
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dbpmp_abi.h1367 uint16_t mdiv; /**< input divider value */ member