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Searched refs:mdiv (Results 1 – 25 of 41) sorted by relevance

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/openbmc/linux/drivers/clk/bcm/
H A Dclk-ns2.c52 .mdiv = REG_VAL(0x18, 0, 8),
58 .mdiv = REG_VAL(0x18, 8, 8),
64 .mdiv = REG_VAL(0x14, 0, 8),
70 .mdiv = REG_VAL(0x14, 8, 8),
76 .mdiv = REG_VAL(0x14, 16, 8),
82 .mdiv = REG_VAL(0x14, 24, 8),
114 .mdiv = REG_VAL(0x18, 0, 8),
120 .mdiv = REG_VAL(0x18, 8, 8),
126 .mdiv = REG_VAL(0x14, 0, 8),
132 .mdiv = REG_VAL(0x14, 8, 8),
[all …]
H A Dclk-sr.c52 .mdiv = REG_VAL(0x18, 0, 9),
58 .mdiv = REG_VAL(0x18, 10, 9),
64 .mdiv = REG_VAL(0x18, 20, 9),
70 .mdiv = REG_VAL(0x1c, 0, 9),
76 .mdiv = REG_VAL(0x1c, 10, 9),
82 .mdiv = REG_VAL(0x1c, 20, 9),
112 .mdiv = REG_VAL(0x18, 0, 9),
118 .mdiv = REG_VAL(0x18, 10, 9),
124 .mdiv = REG_VAL(0x18, 20, 9),
130 .mdiv = REG_VAL(0x1c, 0, 9),
[all …]
H A Dclk-cygnus.c66 .mdiv = REG_VAL(0x20, 0, 8),
72 .mdiv = REG_VAL(0x20, 10, 8),
78 .mdiv = REG_VAL(0x20, 20, 8),
84 .mdiv = REG_VAL(0x24, 0, 8),
90 .mdiv = REG_VAL(0x24, 10, 8),
96 .mdiv = REG_VAL(0x24, 20, 8),
124 .mdiv = REG_VAL(0x8, 0, 8),
130 .mdiv = REG_VAL(0x8, 10, 8),
136 .mdiv = REG_VAL(0x8, 20, 8),
142 .mdiv = REG_VAL(0xc, 0, 8),
[all …]
H A Dclk-iproc-armpll.c109 int mdiv; in __get_mdiv() local
117 mdiv = 1; in __get_mdiv()
122 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; in __get_mdiv()
123 if (mdiv == 0) in __get_mdiv()
124 mdiv = 256; in __get_mdiv()
129 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; in __get_mdiv()
130 if (mdiv == 0) in __get_mdiv()
131 mdiv = 256; in __get_mdiv()
135 mdiv = -EFAULT; in __get_mdiv()
138 return mdiv; in __get_mdiv()
[all …]
H A Dclk-nsp.c51 .mdiv = REG_VAL(0x18, 16, 8),
57 .mdiv = REG_VAL(0x18, 8, 8),
63 .mdiv = REG_VAL(0x18, 0, 8),
69 .mdiv = REG_VAL(0x1c, 16, 8),
75 .mdiv = REG_VAL(0x1c, 8, 8),
81 .mdiv = REG_VAL(0x1c, 0, 8),
108 .mdiv = REG_VAL(0x8, 24, 8),
114 .mdiv = REG_VAL(0x8, 16, 8),
120 .mdiv = REG_VAL(0x8, 8, 8),
H A Dclk-iproc-pll.c617 unsigned int mdiv; in iproc_clk_recalc_rate() local
623 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_recalc_rate()
624 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); in iproc_clk_recalc_rate()
625 if (mdiv == 0) in iproc_clk_recalc_rate()
626 mdiv = 256; in iproc_clk_recalc_rate()
629 rate = parent_rate / (mdiv * 2); in iproc_clk_recalc_rate()
631 rate = parent_rate / mdiv; in iproc_clk_recalc_rate()
677 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_set_rate()
679 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
681 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
[all …]
H A Dclk-iproc.h187 struct iproc_clk_reg_op mdiv; member
/openbmc/linux/drivers/clk/samsung/
H A Dclk-pll.c153 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()
161 fvco *= (mdiv + 8); in samsung_pll2126_recalc_rate()
186 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()
194 fvco *= (2 * (mdiv + 8)); in samsung_pll3000_recalc_rate()
223 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; in samsung_pll35xx_recalc_rate()
231 fvco *= mdiv; in samsung_pll35xx_recalc_rate()
245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
H A Dclk-pll.h52 .mdiv = (_m), \
61 .mdiv = (_m), \
71 .mdiv = (_m), \
81 .mdiv = (_m), \
92 .mdiv = (_m), \
106 unsigned int mdiv; member
/openbmc/linux/drivers/clk/imx/
H A Dclk-pll14xx.c104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
110 fvco *= (mdiv * 65536 + kdiv); in pll14xx_calc_rate()
118 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, in pll1443x_calc_kdiv() argument
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
133 int mdiv, pdiv, sdiv, kdiv; in imx_pll14xx_calc_settings() local
154 t->mdiv = tt->mdiv; in imx_pll14xx_calc_settings()
162 mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); in imx_pll14xx_calc_settings()
168 rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); in imx_pll14xx_calc_settings()
169 rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate); in imx_pll14xx_calc_settings()
172 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); in imx_pll14xx_calc_settings()
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c48 u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; in cm_basic_init() local
58 mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & in cm_basic_init()
62 mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; in cm_basic_init()
63 hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - in cm_basic_init()
80 mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & in cm_basic_init()
84 mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; in cm_basic_init()
85 hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - in cm_basic_init()
175 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
197 mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; in cm_get_main_vco_clk_hz()
200 vco = vco * (CLKMGR_MDIV_CONST + mdiv); in cm_get_main_vco_clk_hz()
[all …]
/openbmc/u-boot/drivers/clk/exynos/
H A Dclk-pll.c22 unsigned long mdiv, sdiv, pdiv; in pll145x_get_rate() local
25 mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; in pll145x_get_rate()
29 fvco *= mdiv; in pll145x_get_rate()
/openbmc/linux/drivers/clk/st/
H A Dclkgen-fsyn.c35 unsigned long mdiv; member
58 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; member
102 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
165 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
554 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
639 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
663 fs_tmp.mdiv = (unsigned long) m; in clk_fs660c32_get_pe()
673 fs->mdiv = m; in clk_fs660c32_get_pe()
719 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
752 params->mdiv = CLKGEN_READ(fs, mdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
[all …]
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-pll-s10.c65 unsigned long arefdiv, reg, mdiv; in agilex_clk_pll_recalc_rate() local
76 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; in agilex_clk_pll_recalc_rate()
78 vco_freq = (unsigned long long)vco_freq * mdiv; in agilex_clk_pll_recalc_rate()
86 unsigned long mdiv; in clk_pll_recalc_rate() local
100 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; in clk_pll_recalc_rate()
101 vco_freq = (unsigned long long)vco_freq * (mdiv + 6); in clk_pll_recalc_rate()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c35 u32 mdiv; member
320 info->mdiv |= 0x80000000; in calc_clk()
321 info->mdiv |= div1D; in calc_clk()
327 info->mdiv |= 0x80000000; in calc_clk()
328 info->mdiv |= div1P << 8; in calc_clk()
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
418 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
H A Dgf100.c35 u32 mdiv; member
307 info->mdiv |= 0x80000000; in calc_clk()
308 info->mdiv |= div1D; in calc_clk()
314 info->mdiv |= 0x80000000; in calc_clk()
315 info->mdiv |= div1P << 8; in calc_clk()
412 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); in gf100_clk_prog_4()
/openbmc/linux/sound/soc/codecs/
H A Dak4375.c279 unsigned int mclk, plm, mdiv, div; in ak4375_dai_set_pll() local
327 mdiv = freq_out / mclk - 1; in ak4375_dai_set_pll()
332 mdiv = freq_out / mclk - 1; in ak4375_dai_set_pll()
337 mdiv = 4; in ak4375_dai_set_pll()
359 snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv); in ak4375_dai_set_pll()
362 ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div); in ak4375_dai_set_pll()
/openbmc/linux/drivers/media/dvb-frontends/
H A Dhorus3a.c172 u8 mdiv = 0; in horus3a_set_params() local
190 mdiv = 1; in horus3a_set_params()
193 mdiv = 0; in horus3a_set_params()
296 data[4] = (u8)(mdiv << 7); in horus3a_set_params()
/openbmc/u-boot/board/synopsys/iot_devkit/
H A Dconfig.mk1 PLATFORM_CPPFLAGS += -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel…
/openbmc/linux/drivers/iio/frequency/
H A Dadf4350.c140 u16 mdiv, r_cnt = 0; in adf4350_set_freq() local
148 mdiv = 75; in adf4350_set_freq()
151 mdiv = 23; in adf4350_set_freq()
187 } while (mdiv > st->r0_int); in adf4350_set_freq()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dctrl.c126 args->v0.min = lo / domain->mdiv; in nvkm_control_mthd_pstate_attr()
127 args->v0.max = hi / domain->mdiv; in nvkm_control_mthd_pstate_attr()
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos4_setup.h340 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
341 | (mdiv << 16) \
/openbmc/linux/drivers/clk/
H A Dclk-versaclock3.c247 u8 mdiv; in vc3_pfd_recalc_rate() local
259 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
270 mdiv = VC3_PLL2_M_DIV(prediv); in vc3_pfd_recalc_rate()
276 mdiv = VC3_PLL3_M_DIV(prediv); in vc3_pfd_recalc_rate()
282 rate = parent_rate / mdiv; in vc3_pfd_recalc_rate()
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dclk.h79 int mdiv; member
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1664 u32 mdiv; in vlv_prepare_pll() local
1694 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); in vlv_prepare_pll()
1695 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); in vlv_prepare_pll()
1696 mdiv |= ((bestn << DPIO_N_SHIFT)); in vlv_prepare_pll()
1697 mdiv |= (1 << DPIO_K_SHIFT); in vlv_prepare_pll()
1704 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); in vlv_prepare_pll()
1705 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
1707 mdiv |= DPIO_ENABLE_CALIBRATION; in vlv_prepare_pll()
1708 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()

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