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Searched refs:mask_results_dq_reg_map (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c52 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_pbs() local
105 mask_results_dq_reg_map[ in ddr3_tip_pbs()
223 mask_results_dq_reg_map[ in ddr3_tip_pbs()
412 mask_results_dq_reg_map[ in ddr3_tip_pbs()
533 mask_results_dq_reg_map in ddr3_tip_pbs()
636 mask_results_dq_reg_map in ddr3_tip_pbs()
H A Dddr3_training_leveling.c412 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_dynamic_per_bit_read_leveling() local
589 mask_results_dq_reg_map in ddr3_tip_dynamic_per_bit_read_leveling()
605 mask_results_dq_reg_map in ddr3_tip_dynamic_per_bit_read_leveling()
1464 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_dynamic_write_leveling_seq() local
1497 mask_results_dq_reg_map[dq_id], 0x1 << 24, in ddr3_tip_dynamic_write_leveling_seq()
1531 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_dynamic_read_leveling_seq() local
1539 mask_results_dq_reg_map[dq_id], 0x1 << 24, in ddr3_tip_dynamic_read_leveling_seq()
1569 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_dynamic_per_bit_read_leveling_seq() local
1577 mask_results_dq_reg_map[dq_id], 0x1 << 24, in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1594 mask_results_dq_reg_map[dq_id], 0x0 << 24, in ddr3_tip_dynamic_per_bit_read_leveling_seq()
H A Dddr3_training_ip_engine.c22 u16 mask_results_dq_reg_map[] = { variable
356 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_ip_training() local
502 mask_results_dq_reg_map[index_cnt], 0, in ddr3_tip_ip_training()
516 mask_results_dq_reg_map in ddr3_tip_ip_training()
541 mask_results_dq_reg_map[index_cnt], in ddr3_tip_ip_training()
708 u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg(); in ddr3_tip_read_training_result() local
743 reg_addr = mask_results_dq_reg_map; in ddr3_tip_read_training_result()
1625 return mask_results_dq_reg_map; in ddr3_tip_get_mask_results_dq_reg()
H A Dddr3_init.h132 extern u16 mask_results_dq_reg_map[];