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Searched refs:malidp_write32_mask (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_dev.c61 malidp_write32_mask(reg, BLK_STATUS, restore, 0); in get_lpu_event()
113 malidp_write32_mask(reg, BLK_STATUS, status, 0); in get_cu_event()
155 malidp_write32_mask(reg, BLK_STATUS, restore, 0); in get_dou_event()
196 malidp_write32_mask(d71->gcu_addr, BLK_STATUS, in d71_irq_handler()
225 malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, in d71_enable_irq()
229 malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK, in d71_enable_irq()
231 malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK, in d71_enable_irq()
233 malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK, in d71_enable_irq()
248 malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK, in d71_disable_irq()
250 malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK, in d71_disable_irq()
[all …]
H A Dd71_component.c211 malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0); in d71_layer_disable()
283 malidp_write32_mask(reg, BLK_CONTROL, ctrl_mask, ctrl); in d71_layer_update()
481 malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl); in d71_wb_layer_update()
516 malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0); in d71_wb_layer_disable()
1088 malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl); in d71_improc_update()
1161 malidp_write32_mask(c->reg, BLK_CONTROL, BS_CTRL_EN, 0); in d71_timing_ctrlr_disable()
/openbmc/linux/drivers/gpu/drm/arm/display/include/
H A Dmalidp_io.h32 malidp_write32_mask(u32 __iomem *base, u32 offset, u32 m, u32 v) in malidp_write32_mask() function