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Searched refs:levels (Results 1 – 25 of 141) sorted by relevance

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/openbmc/qemu/util/
H A Dhbitmap.c98 unsigned long *levels[HBITMAP_LEVELS]; member
117 cur = hbi->cur[i] & hb->levels[i][pos]; in hbitmap_iter_skip_words()
139 cur = hb->levels[i + 1][pos]; in hbitmap_iter_skip_words()
152 hbi->hb->levels[HBITMAP_LEVELS - 1][hbi->pos]; in hbitmap_iter_next()
185 hbi->cur[i] = hb->levels[i][pos] & ~((1UL << bit) - 1); in hbitmap_iter_init()
223 unsigned long *last_lev = hb->levels[HBITMAP_LEVELS - 1]; in hbitmap_next_zero()
442 changed |= hb_set_elem(&hb->levels[level][i], start, next - 1); in hb_set_between()
449 changed |= (hb->levels[level][i] == 0); in hb_set_between()
450 hb->levels[level][i] = ~0UL; in hb_set_between()
453 changed |= hb_set_elem(&hb->levels[level][i], start, last); in hb_set_between()
[all …]
/openbmc/qemu/target/riscv/
H A Dmonitor.c148 int levels, ptidxbits, ptesize, vm, va_bits; in mem_info_svxx() local
166 levels = 2; in mem_info_svxx()
171 levels = 3; in mem_info_svxx()
176 levels = 4; in mem_info_svxx()
181 levels = 5; in mem_info_svxx()
190 va_bits = PGSHIFT + levels * ptidxbits; in mem_info_svxx()
202 walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, in mem_info_svxx()
H A Dcpu_helper.c1234 int levels, ptidxbits, ptesize, vm, widened; in get_physical_address() local
1268 levels = 2; ptidxbits = 10; ptesize = 4; break; in get_physical_address()
1270 levels = 3; ptidxbits = 9; ptesize = 8; break; in get_physical_address()
1272 levels = 4; ptidxbits = 9; ptesize = 8; break; in get_physical_address()
1274 levels = 5; ptidxbits = 9; ptesize = 8; break; in get_physical_address()
1284 int va_bits = PGSHIFT + levels * ptidxbits + widened; in get_physical_address()
1318 int ptshift = (levels - 1) * ptidxbits; in get_physical_address()
1324 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { in get_physical_address()
1593 if ((i != (levels - 1)) || (napot_bits != 4)) { in get_physical_address()
/openbmc/u-boot/drivers/video/
H A Dpwm_backlight.c42 u32 *levels; member
137 if (priv->levels) { in pwm_backlight_set_brightness()
138 level = priv->levels[percent * (priv->num_levels - 1) in pwm_backlight_set_brightness()
210 priv->levels = malloc(len); in pwm_backlight_ofdata_to_platdata()
211 if (!priv->levels) in pwm_backlight_ofdata_to_platdata()
213 dev_read_u32_array(dev, "brightness-levels", priv->levels, in pwm_backlight_ofdata_to_platdata()
216 priv->default_level = priv->levels[index]; in pwm_backlight_ofdata_to_platdata()
217 priv->max_level = priv->levels[count - 1]; in pwm_backlight_ofdata_to_platdata()
/openbmc/qemu/scripts/
H A Dcpu-x86-uarch-abi.py20 levels = [ variable
128 for level in range(len(levels)):
130 want = set(levels[level])
147 for level in range(len(levels)):
185 for level in range(len(levels)):
/openbmc/qemu/hw/core/
H A Dor-irq.c38 s->levels[n] = level; in or_irq_handler()
41 or_level |= s->levels[i]; in or_irq_handler()
53 s->levels[i] = false; in or_irq_reset()
98 VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
109 VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
/openbmc/qemu/hw/intc/
H A Dheathrow_pic.c35 return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask; in heathrow_check_irq()
98 value = pic->levels; in heathrow_read()
124 last_level = (pic->levels & irq_bit) ? 1 : 0; in heathrow_set_irq()
128 pic->levels |= irq_bit; in heathrow_set_irq()
130 pic->levels &= ~irq_bit; in heathrow_set_irq()
147 VMSTATE_UINT32(levels, HeathrowPICState),
/openbmc/bmcweb/src/
H A Dwebserver_cli.cpp26 static constexpr std::array<std::string, 7> levels{ variable
33 const std::string* iter = std::ranges::find(levels, input); in validateLogLevel()
34 if (iter == levels.end()) in validateLogLevel()
44 for (const std::string& prompt : levels) in helpMsg()
/openbmc/qemu/hw/vfio/
H A Dspapr.c37 unsigned int levels; member
304 create.levels = bits_total / bits_per_level; in vfio_spapr_create_window()
306 ddw_levels = scontainer->levels; in vfio_spapr_create_window()
309 ++create.levels; in vfio_spapr_create_window()
312 for ( ; create.levels <= max_levels; ++create.levels) { in vfio_spapr_create_window()
319 if (create.levels > ddw_levels) { in vfio_spapr_create_window()
342 create.levels, in vfio_spapr_create_window()
528 scontainer->levels = info.ddw.levels; in vfio_spapr_container_setup()
/openbmc/webui-vue/src/assets/styles/bmc/helpers/
H A D_functions.scss19 // Positive levels darken (mix with black), negative levels lighten (mix with white)
/openbmc/qemu/include/hw/
H A Dor-irq.h44 bool levels[MAX_OR_LINES]; member
/openbmc/qemu/include/hw/intc/
H A Dheathrow_pic.h38 uint32_t levels; member
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-bsp/bolt/
H A Dbolt_0.9.6.bb2 DESCRIPTION = "Userspace system daemon to enable security levels for Thunderbolt on GNU/Linux"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/oprofile/oprofile/
H A D0007-oprofile-doesn-t-want-GNU-levels-of-automake-strictn.patch4 Subject: [PATCH 07/10] oprofile doesn't want GNU-levels of automake strictness
/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c259 unsigned char levels; in riscv_iommu_spa_fetch() member
314 sc[pass].levels = 0; in riscv_iommu_spa_fetch()
323 sc[pass].levels = 2; in riscv_iommu_spa_fetch()
334 sc[pass].levels = 0; in riscv_iommu_spa_fetch()
343 sc[pass].levels = 3; in riscv_iommu_spa_fetch()
352 sc[pass].levels = 4; in riscv_iommu_spa_fetch()
361 sc[pass].levels = 5; in riscv_iommu_spa_fetch()
382 (sc[pass].levels - 1 - sc[pass].step); in riscv_iommu_spa_fetch()
458 sc[pass].step = sc[pass].levels; in riscv_iommu_spa_fetch()
463 if (pass && sc[0].step != sc[0].levels) { in riscv_iommu_spa_fetch()
[all …]
/openbmc/qemu/docs/specs/
H A Dppc-spapr-numa.rst51 the NUMA levels for the platform.
67 three NUMA levels:
77 P2 processors, we would have the following NUMA levels:
150 the distance of the previous level, and the maximum amount of levels is
156 * resources two NUMA levels apart: 40
157 * resources three NUMA levels apart: 80
158 * resources four NUMA levels apart: 160
168 for 4 distinct NUMA distance values based on the NUMA levels
171 NUMA levels, granting user flexibility
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/wavemon/
H A Dwavemon_0.9.6.bb4 allows you to watch signal and noise levels, packet \
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/opencv/opencv/
H A D0008-Do-not-embed-build-directory-in-binaries.patch107 for (int levels = 0; levels < 3; ++levels)
/openbmc/openbmc/poky/meta/classes-recipe/
H A Dqemu.bbclass26 # qemu-arm default CPU supports all required architecture levels.
/openbmc/u-boot/arch/arm/dts/
H A Dsun5i-a13-utoo-p66.dts73 /* Note levels of 10 / 20% result in backlight off */
74 brightness-levels = <0 30 40 50 60 70 80 90 100>;
H A Dtegra20-colibri.dts118 brightness-levels = <255 128 64 32 16 8 4 0>;
/openbmc/openbmc/poky/bitbake/lib/bb/tests/
H A Dcow.py71 levels = int(match.group(2))
72 self.assertEqual(levels, expected_levels, "wrong # levels in str: '{0}'".format(s))
/openbmc/qemu/docs/system/
H A Dcpu-models-x86.rst.inc42 ABI compatibility levels for CPU models
45 The x86_64 architecture has a number of `ABI compatibility levels`_
49 table that follows illustrates which ABI compatibility levels
56 .. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
58 .. csv-table:: x86-64 ABI compatibility levels
85 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
/openbmc/openbmc/poky/meta/recipes-extended/at/
H A Dat_3.2.5.bb4 the system load levels drop to a particular level."
/openbmc/openbmc/poky/meta/recipes-support/attr/
H A Dacl_2.3.2.bb2 DESCRIPTION = "ACL allows you to provide different levels of access to files \

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