| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_fixed_vs_pe_retimer.c | 75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
252 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy()
291 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence_legacy()
317 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
447 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
467 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
598 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence()
637 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence()
663 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
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| H A D | link_dp_capability.c | 437 switch (lane_count) { in reduce_lane_count()
486 switch (lane_count) { in increase_lane_count()
539 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
549 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
567 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; in decide_fallback_link_setting_max_bw_policy()
611 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
621 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
630 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
646 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
865 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { in decide_edp_link_settings_with_dsc()
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| H A D | link_dp_training_8b_10b.c | 103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
163 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
228 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
267 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
279 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
334 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
340 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
341 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
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| H A D | link_dp_training_dpia.c | 298 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
403 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
409 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
468 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
511 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
623 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
717 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent()
722 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
771 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_transparent() local
804 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_transparent()
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| H A D | link_dp_training.c | 172 lt_settings->link_settings.lane_count, in dp_log_training_result()
463 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
1048 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1094 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1104 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1129 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1348 enum dc_lane_count lane_count = in perform_post_lt_adj_req_sequence() local
1349 lt_settings->link_settings.lane_count; in perform_post_lt_adj_req_sequence()
1381 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_post_lt_adj_req_sequence()
1560 (cur_link_settings.lane_count <= LANE_COUNT_ONE); in perform_link_training_with_retries()
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| H A D | link_dp_irq_handler.c | 57 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
63 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
262 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
263 link->verified_link_cap.lane_count; in dp_handle_link_loss()
354 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
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| /openbmc/linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_core.c | 264 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
321 lane_count); in analogix_dp_link_start()
350 int lane_count) in analogix_dp_channel_eq_ok() argument
446 int lane, lane_count; in analogix_dp_get_adjust_training_lane() local
449 lane_count = dp->link_train.lane_count; in analogix_dp_get_adjust_training_lane()
469 int lane, lane_count, retval; in analogix_dp_process_clock_recovery() local
475 lane_count = dp->link_train.lane_count; in analogix_dp_process_clock_recovery()
541 int lane, lane_count, retval; in analogix_dp_process_equalizer_training() local
547 lane_count = dp->link_train.lane_count; in analogix_dp_process_equalizer_training()
585 dp->link_train.lane_count); in analogix_dp_process_equalizer_training()
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| /openbmc/u-boot/drivers/video/ |
| H A D | logicore_dp_tx.c | 165 u8 lane_count; member
724 if (lane_count != LANE_COUNT_SET_1 && in is_lane_count_valid()
725 lane_count != LANE_COUNT_SET_2 && in is_lane_count_valid()
726 lane_count != LANE_COUNT_SET_4) in is_lane_count_valid()
901 dp_tx->link_config.lane_count = lane_count; in set_lane_count()
911 val |= dp_tx->link_config.lane_count; in set_lane_count()
1215 switch (lane_count) { in check_clock_recovery()
1260 switch (lane_count) { in check_channel_equalization()
1280 switch (lane_count) { in check_channel_equalization()
1625 switch (dp_tx->link_config.lane_count) { in trainig_state_adjust_lane_count()
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| H A D | logicore_dp_tx_regif.h | 378 static inline u32 phy_status_lanes_ready_mask(u8 lane_count) in phy_status_lanes_ready_mask() argument
380 if (lane_count > 2) in phy_status_lanes_ready_mask()
383 if (lane_count == 2) in phy_status_lanes_ready_mask()
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| /openbmc/u-boot/drivers/video/tegra124/ |
| H A D | dp.c | 431 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()
456 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
462 if (cfg->lane_count == 1) { in _tegra_dp_lower_link_config()
466 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
623 (12 / link_cfg->lane_count); in tegra_dc_dp_calc_config()
638 link_cfg->lane_count) - 4; in tegra_dc_dp_calc_config()
797 u32 n_lanes = cfg->lane_count; in tegra_dp_channel_eq_status()
1238 u8 lane_count; in tegra_dc_dp_fast_link_training() local
1294 link_bw, lane_count); in tegra_dc_dp_fast_link_training()
1310 u8 lane_count; in tegra_dp_do_link_training() local
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| H A D | sor.c | 212 u32 lane_count, int pu) in tegra_dc_sor_power_dplanes() argument
220 switch (lane_count) { in tegra_dc_sor_power_dplanes()
236 tegra_dc_sor_set_lane_count(dev, lane_count); in tegra_dc_sor_power_dplanes()
387 u8 *lane_count) in tegra_dc_sor_read_link_config() argument
400 *lane_count = 0; in tegra_dc_sor_read_link_config()
403 *lane_count = 1; in tegra_dc_sor_read_link_config()
406 *lane_count = 2; in tegra_dc_sor_read_link_config()
409 *lane_count = 4; in tegra_dc_sor_read_link_config()
432 switch (lane_count) { in tegra_dc_sor_set_lane_count()
893 switch (link_cfg->lane_count) { in tegra_dc_sor_power_down_unused_lanes()
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_link_training.c | 467 crtc_state->lane_count, in intel_dp_get_adjust_train()
474 crtc_state->lane_count, in intel_dp_get_adjust_train()
509 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
579 crtc_state->lane_count, in intel_dp_set_signal_levels()
586 crtc_state->lane_count, in intel_dp_set_signal_levels()
621 return ret == crtc_state->lane_count; in intel_dp_update_link_train()
694 u8 lane_count = crtc_state->lane_count; in intel_dp_update_link_bw_set() local
701 u8 link_config[] = { link_bw, lane_count }; in intel_dp_update_link_bw_set()
1003 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
1011 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
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| H A D | intel_dp.h | 42 int link_rate, int lane_count);
44 int link_rate, u8 lane_count);
111 u32 link_clock, u32 lane_count,
122 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
124 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
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| H A D | intel_dpio_phy.c | 575 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
583 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
705 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
718 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
771 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
797 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
814 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
880 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
924 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
933 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
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| H A D | vlv_dsi.c | 56 8 * 100), lane_count); in txbyteclkhs()
63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1016 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1068 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1121 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1123 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1125 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1217 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
1240 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
1243 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
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| H A D | intel_combo_phy.c | 263 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
270 switch (lane_count) { in intel_combo_phy_power_up_lanes()
281 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
288 switch (lane_count) { in intel_combo_phy_power_up_lanes()
298 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
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| H A D | vlv_dsi_pll.c | 48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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| H A D | intel_combo_phy.h | 18 int lane_count, bool lane_reversal);
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| /openbmc/linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.h | 96 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
98 return (lane_count == 1 || in is_lane_count_valid()
99 lane_count == 2 || in is_lane_count_valid()
100 lane_count == 4); in is_lane_count_valid()
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk_edp.c | 326 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
367 for (lane = 0; lane < lane_count; lane++) { in rk_edp_clock_recovery()
386 for (lane = 0; lane < lane_count; lane++) { in rk_edp_channel_eq()
425 for (lane = 0; lane < lane_count; lane++) { in edp_get_adjust_train()
484 edp->link_train.lane_count); in rk_edp_link_train_cr()
497 edp->link_train.lane_count); in rk_edp_link_train_cr()
506 if (i == edp->link_train.lane_count) { in rk_edp_link_train_cr()
566 edp->link_train.lane_count); in rk_edp_link_train_ce()
603 edp->link_train.lane_count); in rk_edp_init_training()
612 if (edp->link_train.lane_count == 0) { in rk_edp_init_training()
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| /openbmc/linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 262 uint8_t lane_count; member
898 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
911 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
917 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
991 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1008 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1011 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1055 switch (intel_dp->lane_count) { in cdv_intel_dp_mode_set()
1388 intel_dp->lane_count); in cdv_intel_dplink_set_level()
1390 if (ret != intel_dp->lane_count) { in cdv_intel_dplink_set_level()
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| /openbmc/linux/drivers/gpu/drm/bridge/ |
| H A D | parade-ps8622.c | 54 u32 lane_count; member
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
490 &ps8622->lane_count)) { in ps8622_probe()
491 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
492 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
495 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dio_link_encoder.c | 475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
658 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
680 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 104 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
111 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
196 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
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| /openbmc/linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dp.c | 74 int lane_count; member
1149 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1156 .lanes = lane_count, in mtk_dp_phy_configure()
1342 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1375 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1401 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1726 lane_count = lane_count / 2; in mtk_dp_training()
1728 if (lane_count == 0) in mtk_dp_training()
1751 if (lane_count == 0) in mtk_dp_training()
1753 lane_count /= 2; in mtk_dp_training()
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