431 	      link_cfg->lane_count);  in tegra_dc_dp_dump_link_cfg()
456 		cfg->lane_count /= 2;  in _tegra_dp_lower_link_config()
462 		if (cfg->lane_count == 1) {  in _tegra_dp_lower_link_config()
464 			cfg->lane_count = cfg->max_lane_count;  in _tegra_dp_lower_link_config()
466 			cfg->lane_count /= 2;  in _tegra_dp_lower_link_config()
474 	return (cfg->lane_count > 0) ? 0 : -ENOLINK;  in _tegra_dp_lower_link_config()
507 	if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ ||  in tegra_dc_dp_calc_config()
512 		(u64)link_rate * 8 * link_cfg->lane_count)  in tegra_dc_dp_calc_config()
520 	do_div(ratio_f, link_rate * link_cfg->lane_count);  in tegra_dc_dp_calc_config()
600 			       (8 * link_cfg->lane_count);  in tegra_dc_dp_calc_config()
623 			(12 / link_cfg->lane_count);  in tegra_dc_dp_calc_config()
638 			link_cfg->lane_count) - 4;  in tegra_dc_dp_calc_config()
707 	link_cfg->lane_count = link_cfg->max_lane_count;  in tegra_dc_dp_init_max_link_cfg()
753 	dpcd_data = link_cfg->lane_count;  in tegra_dp_set_lane_count()
760 	tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);  in tegra_dp_set_lane_count()
774 	for (lane = 0; lane < cfg->lane_count; ++lane) {  in tegra_dc_dp_link_trained()
797 	u32 n_lanes = cfg->lane_count;  in tegra_dp_channel_eq_status()
841 	u32 n_lanes = cfg->lane_count;  in tegra_dp_clock_recovery_status()
868 	u32 n_lanes = cfg->lane_count;  in tegra_dp_lt_adjust()
930 	if (link_cfg->lane_count == 0) {  in tegra_dp_link_config()
1009 	u32 n_lanes = cfg->lane_count;  in tegra_dp_lt_config()
1126 	u32 n_lanes = cfg->lane_count;  in tegra_dp_channel_eq()
1174 	u32 n_lanes = cfg->lane_count;  in tegra_dp_clk_recovery()
1238 	u8	lane_count;  in tegra_dc_dp_fast_link_training()  local
1244 	u32	mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);  in tegra_dc_dp_fast_link_training()
1255 	for (j = 0; j < link_cfg->lane_count; ++j)  in tegra_dc_dp_fast_link_training()
1275 	for (j = 0; j < link_cfg->lane_count; ++j)  in tegra_dc_dp_fast_link_training()
1292 		tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);  in tegra_dc_dp_fast_link_training()
1294 		      link_bw, lane_count);  in tegra_dc_dp_fast_link_training()
1299 	      link_cfg->link_bw, link_cfg->lane_count);  in tegra_dc_dp_fast_link_training()
1310 	u8	lane_count;  in tegra_dp_do_link_training()  local
1339 	tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);  in tegra_dp_do_link_training()
1342 	    (link_cfg->lane_count == lane_count))  in tegra_dp_do_link_training()
1370 	temp_cfg.lane_count = temp_cfg.max_lane_count;  in tegra_dc_dp_explore_link_cfg()