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Searched refs:ixSQ_WAVE_GPR_ALLOC (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h78 #define ixSQ_WAVE_GPR_ALLOC 0x0015 macro
H A Dgfx_7_2_d.h1938 #define ixSQ_WAVE_GPR_ALLOC 0x15 macro
H A Dgfx_7_0_d.h1917 #define ixSQ_WAVE_GPR_ALLOC 0x15 macro
H A Dgfx_8_1_d.h2105 #define ixSQ_WAVE_GPR_ALLOC 0x15 macro
H A Dgfx_8_0_d.h2137 #define ixSQ_WAVE_GPR_ALLOC 0x15 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v6_0_read_wave_data()
H A Dgfx_v7_0.c4124 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v7_0_read_wave_data()
H A Dgfx_v9_4_3.c589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v9_4_3_read_wave_data()
H A Dgfx_v11_0.c796 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v11_0_read_wave_data()
H A Dgfx_v8_0.c5230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v8_0_read_wave_data()
H A Dgfx_v9_0.c1783 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v9_0_read_wave_data()
H A Dgfx_v10_0.c4288 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v10_0_read_wave_data()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7101 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_9_4_3_offset.h7411 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_9_1_offset.h7309 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_9_4_2_offset.h7649 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_9_2_1_offset.h7348 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_10_1_0_offset.h11180 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_11_0_3_offset.h12057 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_11_0_0_offset.h11640 #define ixSQ_WAVE_GPR_ALLOC … macro
H A Dgc_10_3_0_offset.h13426 #define ixSQ_WAVE_GPR_ALLOC … macro