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Searched refs:ixGRA03 (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h304 #define ixGRA03 0x0003 macro
H A Ddce_8_0_d.h5103 #define ixGRA03 0x3 macro
H A Ddce_10_0_d.h5986 #define ixGRA03 0x3 macro
H A Ddce_11_0_d.h6063 #define ixGRA03 0x3 macro
H A Ddce_11_2_d.h7737 #define ixGRA03 0x3 macro
H A Ddce_12_0_offset.h18176 #define ixGRA03 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7225 #define ixGRA03 macro
H A Ddcn_3_0_1_offset.h12068 #define ixGRA03 macro
H A Ddcn_2_1_0_offset.h12672 #define ixGRA03 macro
H A Ddcn_1_0_offset.h12807 #define ixGRA03 macro
H A Ddcn_3_1_2_offset.h13882 #define ixGRA03 macro
H A Ddcn_3_2_1_offset.h13358 #define ixGRA03 macro
H A Ddcn_3_1_5_offset.h13988 #define ixGRA03 macro
H A Ddcn_3_1_4_offset.h118 #define ixGRA03 macro
H A Ddcn_3_2_0_offset.h13379 #define ixGRA03 macro
H A Ddcn_3_1_6_offset.h14479 #define ixGRA03 macro
H A Ddcn_3_0_2_offset.h14961 #define ixGRA03 macro
H A Ddcn_2_0_0_offset.h16336 #define ixGRA03 macro
H A Ddcn_3_0_0_offset.h16685 #define ixGRA03 macro