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Searched refs:ixATTR05 (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h31 #define ixATTR05 0x0005 macro
H A Ddce_8_0_d.h5117 #define ixATTR05 0x5 macro
H A Ddce_10_0_d.h6000 #define ixATTR05 0x5 macro
H A Ddce_11_0_d.h6077 #define ixATTR05 0x5 macro
H A Ddce_11_2_d.h7751 #define ixATTR05 0x5 macro
H A Ddce_12_0_offset.h18191 #define ixATTR05 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7240 #define ixATTR05 … macro
H A Ddcn_3_0_1_offset.h12083 #define ixATTR05 … macro
H A Ddcn_1_0_offset.h12822 #define ixATTR05 … macro
H A Ddcn_2_1_0_offset.h12687 #define ixATTR05 … macro
H A Ddcn_3_1_2_offset.h13897 #define ixATTR05 … macro
H A Ddcn_3_1_5_offset.h14003 #define ixATTR05 … macro
H A Ddcn_3_1_4_offset.h133 #define ixATTR05 … macro
H A Ddcn_3_2_1_offset.h13373 #define ixATTR05 … macro
H A Ddcn_3_2_0_offset.h13394 #define ixATTR05 … macro
H A Ddcn_3_0_2_offset.h14976 #define ixATTR05 … macro
H A Ddcn_3_1_6_offset.h14494 #define ixATTR05 … macro
H A Ddcn_2_0_0_offset.h16351 #define ixATTR05 … macro
H A Ddcn_3_0_0_offset.h16700 #define ixATTR05 … macro