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Searched refs:isr (Results 1 – 25 of 111) sorted by relevance

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/openbmc/u-boot/drivers/i2c/
H A Dast2600_i2c.c22 u32 isr; member
117 u32 cmd, isr; in ast2600_i2c_read_data() local
133 ret = readl_poll_timeout(&priv->regs->isr, isr, in ast2600_i2c_read_data()
134 isr & AST2600_I2CM_PKT_DONE, in ast2600_i2c_read_data()
142 writel(AST2600_I2CM_PKT_DONE, &priv->regs->isr); in ast2600_i2c_read_data()
144 if (isr & AST2600_I2CM_TX_NAK) in ast2600_i2c_read_data()
155 u32 cmd, isr; in ast2600_i2c_write_data() local
161 ret = readl_poll_timeout(&priv->regs->isr, isr, in ast2600_i2c_write_data()
162 isr & AST2600_I2CM_PKT_DONE, in ast2600_i2c_write_data()
166 if (isr & AST2600_I2CM_TX_NAK) in ast2600_i2c_write_data()
[all …]
H A Dmv_i2c.c39 u32 isr; member
50 u32 isr; member
84 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ in i2c_reset()
98 int timeout = 1000, isr; in i2c_isr_set_cleared() local
101 isr = readl(&base->isr); in i2c_isr_set_cleared()
105 } while (((isr & set_mask) != set_mask) in i2c_isr_set_cleared()
106 || ((isr & cleared_mask) != 0)); in i2c_isr_set_cleared()
158 writel(readl(&base->isr) | ISR_ITE, &base->isr); in i2c_transfer()
193 writel(readl(&base->isr) | ISR_IRF, &base->isr); in i2c_transfer()
232 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)); in i2c_transfer()
/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c160 s->isr |= R_ISR_TEACK_MASK; in stm32l4x5_update_isr()
162 s->isr &= ~R_ISR_TEACK_MASK; in stm32l4x5_update_isr()
166 s->isr |= R_ISR_REACK_MASK; in stm32l4x5_update_isr()
168 s->isr &= ~R_ISR_REACK_MASK; in stm32l4x5_update_isr()
174 if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || in stm32l4x5_update_irq()
175 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || in stm32l4x5_update_irq()
176 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
177 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || in stm32l4x5_update_irq()
178 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || in stm32l4x5_update_irq()
179 ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || in stm32l4x5_update_irq()
[all …]
H A Dipoctal232.c114 uint8_t isr; member
151 VMSTATE_UINT8(isr, SCC2698Block),
186 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { in update_irq()
212 blk->isr |= ISR_TXRDY(channel); in write_cr()
217 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
236 blk->isr &= ~ISR_RXRDY(channel); in write_cr()
241 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
249 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB); in write_cr()
271 uint8_t old_isr = blk->isr; in io_read()
295 blk->isr &= ~ISR_RXRDY(channel); in io_read()
[all …]
H A Dmcf_uart.c28 uint8_t isr; member
73 s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT); in OBJECT_DECLARE_SIMPLE_TYPE()
75 s->isr |= MCF_UART_TxINT; in OBJECT_DECLARE_SIMPLE_TYPE()
78 s->isr |= MCF_UART_RxINT; in OBJECT_DECLARE_SIMPLE_TYPE()
80 qemu_set_irq(s->irq, (s->isr & s->imr) != 0); in OBJECT_DECLARE_SIMPLE_TYPE()
115 return s->isr; in mcf_uart_read()
163 s->isr &= ~MCF_UART_DBINT; in mcf_do_command()
245 s->isr = 0; in mcf_uart_reset()
272 s->isr |= MCF_UART_DBINT; in mcf_uart_event()
/openbmc/qemu/hw/gpio/
H A Dimx_gpio.c65 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0); in imx_gpio_update_int()
66 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0); in imx_gpio_update_int()
68 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0); in imx_gpio_update_int()
84 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
91 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
97 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
179 reg_value = s->isr; in imx_gpio_read()
240 s->isr &= ~value; in imx_gpio_write()
280 VMSTATE_UINT32(isr, IMXGPIOState),
302 s->isr = 0; in imx_gpio_reset()
H A Dzaurus.c49 uint16_t isr; member
99 return s->isr; in scoop_read()
143 s->isr = value; in scoop_write()
240 VMSTATE_UINT16(isr, ScoopInfo),
/openbmc/u-boot/drivers/usb/gadget/
H A Daspeed_usbtty.c448 u32 isr = ast_udc_read(AST_VHUB_ISR); in udc_irq() local
452 if (!isr) in udc_irq()
455 if (isr & ISR_BUS_RESET) { in udc_irq()
461 if (isr & ISR_BUS_SUSPEND) { in udc_irq()
467 if (isr & ISR_SUSPEND_RESUME) { in udc_irq()
473 if (isr & ISR_HUB_EP0_IN_ACK_STALL) { in udc_irq()
479 if (isr & ISR_HUB_EP0_OUT_ACK_STALL) { in udc_irq()
485 if (isr & ISR_HUB_EP0_OUT_NAK) { in udc_irq()
490 if (isr & ISR_HUB_EP0_IN_DATA_NAK) { in udc_irq()
495 if (isr & ISR_HUB_EP0_SETUP) { in udc_irq()
[all …]
H A Daspeed_udc.c928 u32 isr = readl(base + AST_VHUB_ISR); in aspeed_udc_isr() local
932 isr &= 0x3ffff; in aspeed_udc_isr()
933 if (!isr) in aspeed_udc_isr()
937 if (isr & ISR_BUS_RESET) { in aspeed_udc_isr()
942 if (isr & ISR_BUS_SUSPEND) { in aspeed_udc_isr()
947 if (isr & ISR_SUSPEND_RESUME) { in aspeed_udc_isr()
952 if (isr & ISR_HUB_EP0_IN_ACK_STALL) { in aspeed_udc_isr()
958 if (isr & ISR_HUB_EP0_OUT_ACK_STALL) { in aspeed_udc_isr()
964 if (isr & ISR_HUB_EP0_OUT_NAK) { in aspeed_udc_isr()
969 if (isr & ISR_HUB_EP0_IN_DATA_NAK) { in aspeed_udc_isr()
[all …]
/openbmc/qemu/tests/qtest/
H A Dbcm2835-dma-test.c53 int isr = readl(dma_base + BCM2708_DMA_INT_STATUS); in bcm2835_dma_test_interrupt() local
54 g_assert_cmpint(isr, ==, 0); in bcm2835_dma_test_interrupt()
86 isr = readl(RASPI3_DMA_BASE + BCM2708_DMA_INT_STATUS); in bcm2835_dma_test_interrupt()
87 g_assert_cmpint(isr, ==, 1 << dma_c); in bcm2835_dma_test_interrupt()
H A Dstm32l4x5_usart-test.c307 uint32_t isr; in test_ack() local
319 isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); in test_ack()
320 g_assert_false(isr & R_ISR_TEACK_MASK); in test_ack()
321 g_assert_false(isr & R_ISR_REACK_MASK); in test_ack()
328 isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); in test_ack()
329 g_assert_true(isr & R_ISR_TEACK_MASK); in test_ack()
330 g_assert_true(isr & R_ISR_REACK_MASK); in test_ack()
/openbmc/u-boot/drivers/net/
H A Dne2000_base.c248 int len, start_page, pkt_len, i, isr; in dp83902a_send() local
349 DP_IN(base, DP_ISR, isr); in dp83902a_send()
350 } while ((isr & DP_ISR_RDC) == 0); in dp83902a_send()
569 u8 isr; in dp83902a_Overflow() local
599 DP_IN(base, DP_ISR, isr); in dp83902a_Overflow()
600 if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { in dp83902a_Overflow()
610 u8 isr; in dp83902a_poll() local
613 DP_IN(base, DP_ISR, isr); in dp83902a_poll()
614 while (0 != isr) { in dp83902a_poll()
620 if (isr & DP_ISR_CNT) { in dp83902a_poll()
[all …]
/openbmc/qemu/hw/net/
H A Dne2000.c128 s->isr = ENISR_RESET; in ne2000_reset()
142 int isr; in ne2000_update_irq() local
143 isr = (s->isr & s->imr) & 0x7f; in ne2000_update_irq()
146 isr ? 1 : 0, s->isr, s->imr); in ne2000_update_irq()
148 qemu_set_irq(s->irq, (isr != 0)); in ne2000_update_irq()
254 s->isr |= ENISR_RX; in ne2000_receive()
271 s->isr &= ~ENISR_RESET; in ne2000_ioport_write()
275 s->isr |= ENISR_RDC; in ne2000_ioport_write()
290 s->isr |= ENISR_TX; in ne2000_ioport_write()
346 s->isr &= ~(val & 0x7f); in ne2000_ioport_write()
[all …]
H A Dftgmac100.c269 qemu_set_irq(s->irq, s->isr & s->ier); in ftgmac100_update_irq()
510 s->isr |= FTGMAC100_INT_XPKT_LOST; in ftgmac100_insert_vlan()
518 s->isr |= FTGMAC100_INT_XPKT_LOST; in ftgmac100_insert_vlan()
547 s->isr |= FTGMAC100_INT_NO_NPTXBUF; in ftgmac100_do_tx()
572 s->isr |= FTGMAC100_INT_XPKT_LOST; in ftgmac100_do_tx()
585 s->isr |= FTGMAC100_INT_AHB_ERR; in ftgmac100_do_tx()
618 s->isr |= FTGMAC100_INT_XPKT_ETH; in ftgmac100_do_tx()
622 s->isr |= FTGMAC100_INT_XPKT_FIFO; in ftgmac100_do_tx()
692 s->isr = 0; in ftgmac100_do_reset()
734 return s->isr; in ftgmac100_read()
[all …]
/openbmc/u-boot/arch/microblaze/cpu/
H A Dinterrupts.c57 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in enable_one_interrupt()
72 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in disable_one_interrupt()
110 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in intc_init()
166 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in interrupt_handler()
180 debug("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr, in interrupt_handler()
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_mlc.c53 u32 isr; member
189 int status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_dev_ready()
246 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_read_page_hwecc()
294 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_read_page_raw()
346 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_read_oob()
400 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_write_page_hwecc()
412 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_write_page_hwecc()
493 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_write_oob()
519 status = readl(&lpc32xx_nand_mlc_registers->isr); in lpc32xx_waitfunc()
643 status = readl(&lpc32xx_nand_mlc_registers->isr); in read_single_page()
/openbmc/qemu/hw/intc/
H A Dloongson_liointc.c53 uint32_t isr; member
68 p->isr = p->pin_state; in update_irq()
71 p->isr &= p->ien; in update_irq()
80 if (!(p->isr & (1 << irq))) { in update_irq()
140 r = p->isr; in liointc_read()
H A Di8259.c87 mask = s->isr; in pic_get_irq()
164 s->isr |= (1 << irq); in pic_intack()
264 priority = get_priority(s, s->isr); in pic_ioport_write()
267 s->isr &= ~(1 << irq); in pic_ioport_write()
276 s->isr &= ~(1 << irq); in pic_ioport_write()
285 s->isr &= ~(1 << irq); in pic_ioport_write()
339 ret = s->isr; in pic_ioport_read()
H A Di8259_common.c41 s->isr = 0; in pic_reset_common()
141 s->master ? 0 : 1, s->irr, s->imr, s->isr, in pic_print_info()
175 VMSTATE_UINT8(isr, PICCommonState),
/openbmc/qemu/hw/timer/
H A Dmss-timer.c62 bool isr, ier; in timer_update_irq() local
64 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); in timer_update_irq()
66 qemu_set_irq(st->irq, (ier && isr)); in timer_update_irq()
92 int isr; in timer_read() local
113 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); in timer_read()
115 ret = ier & isr; in timer_read()
H A Dhpet.c87 uint64_t isr; /* interrupt status reg */ member
210 s->isr |= mask; in update_irq()
212 s->isr &= ~mask; in update_irq()
336 VMSTATE_UINT64(isr, HPETState),
415 if (s->isr & (1 << t->tn)) { in hpet_del_timer()
447 return s->isr >> shift; in hpet_ram_read()
503 if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))) { in hpet_ram_write()
529 cleared = new_val & s->isr; in hpet_ram_write()
570 && (s->isr & (1 << timer_id))) { in hpet_ram_write()
/openbmc/u-boot/drivers/spi/
H A Dzynq_spi.c42 u32 isr; /* 0x04 */ member
108 while (readl(&regs->isr) & in zynq_spi_init_hw()
113 writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr); in zynq_spi_init_hw()
248 status = readl(&regs->isr); in zynq_spi_xfer()
254 status = readl(&regs->isr); in zynq_spi_xfer()
258 status = readl(&regs->isr); in zynq_spi_xfer()
263 status = readl(&regs->isr); in zynq_spi_xfer()
H A Dzynq_qspi.c55 u32 isr; /* 0x04 */ member
135 while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) in zynq_qspi_init_hw()
139 writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr); in zynq_qspi_init_hw()
313 if (!(readl(&regs->isr) in zynq_qspi_fill_tx_fifo()
349 status = readl(&regs->isr); in zynq_qspi_irq_poll()
358 writel(status, &regs->isr); in zynq_qspi_irq_poll()
/openbmc/qemu/hw/i386/kvm/
H A Di8259.c55 s->isr = kpic->isr; in kvm_pic_get()
83 kpic->isr = s->isr; in kvm_pic_put()
/openbmc/qemu/tests/qtest/libqos/
H A Dvirtio-mmio.c95 uint32_t isr; in qvirtio_mmio_get_queue_isr_status() local
97 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1; in qvirtio_mmio_get_queue_isr_status()
98 if (isr != 0) { in qvirtio_mmio_get_queue_isr_status()
109 uint32_t isr; in qvirtio_mmio_get_config_isr_status() local
111 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2; in qvirtio_mmio_get_config_isr_status()
112 if (isr != 0) { in qvirtio_mmio_get_config_isr_status()

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