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Searched refs:isb (Results 1 – 25 of 43) sorted by relevance

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/openbmc/u-boot/arch/arm/lib/
H A Dgic_64.S99 isb
117 isb
121 isb
124 isb
130 isb
133 isb
137 isb
173 isb
H A Dcache.c116 isb(); in invalidate_l2_cache()
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c163 isb(); /* Make sure instruction stream sees it */ in action_cache_range()
195 isb(); /* Make sure instruction stream sees it */ in action_dcache_all()
214 isb(); /* Make sure instruction stream sees it */ in dcache_enable()
232 isb(); /* Make sure instruction stream sees it */ in dcache_disable()
303 isb(); /* Make sure instruction stream sees it */ in invalidate_icache_all()
316 isb(); /* Make sure instruction stream sees it */ in icache_enable()
329 isb(); /* flush pipeline */ in icache_disable()
331 isb(); /* subsequent instructions fetch see cache disable effect */ in icache_disable()
H A Dmpu.c29 isb(); /* Make sure instruction stream sees it */ in enable_mpu()
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dtlb.S22 isb
26 isb
30 isb
H A Dgeneric_timer.c39 isb(); in timer_read_counter()
66 isb(); in timer_read_counter()
81 isb(); in timer_read_counter()
H A Dcache.S28 isb /* sync change of cssidr_el1 */
101 isb
185 isb sy
239 0: isb
254 0: isb
263 0: isb
/openbmc/u-boot/arch/arm/include/asm/arch-armv7/
H A Dgenerictimer.h36 isb
39 1 : isb
45 isb
/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c66 isb(); in __mdelay()
70 isb(); in __mdelay()
75 isb(); in __mdelay()
206 isb(); in cp15_write_scr()
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dmpu_v7r.c41 isb(); in disable_mpu()
52 isb(); in enable_mpu()
H A Dnonsec_virt.S49 isb
64 isb
71 isb
88 isb
202 isb
H A Dcache_v7_asm.S40 isb @ isb to sych the new cssr&csidr
71 isb
110 isb @ isb to sych the new cssr&csidr
141 isb
H A Dcache_v7.c92 isb(); in v7_inval_tlb()
199 isb(); in invalidate_icache_all()
H A Dpsci.S161 isb
206 isb @ isb to sych the new cssr&csidr
234 isb
243 isb
253 isb
268 isb
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-suspend.S48 isb
62 isb
/openbmc/u-boot/arch/arm/include/asm/
H A Dcache.h27 isb(); in invalidate_l2_cache()
H A Dbarriers.h46 #define isb() ISB macro
H A Darmv7.h81 isb(); in write_l2ctlr()
H A Dsystem.h392 isb(); in set_cr()
406 isb(); in set_dacr()
/openbmc/u-boot/arch/arm/mach-zynq/
H A Dlowlevel_init.S17 isb
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Drmr_switch.S41 isb sy
45 isb sy
/openbmc/qemu/tests/tcg/aarch64/system/
H A Dboot.S204 isb /* Synchronization barrier */
322 isb
341 isb
H A Dmte.S64 isb
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S81 isb
223 isb
285 isb
303 isb
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dcpu.h92 isb(); in writefr_extra_feature_reg()

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