1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2ea0364f1SPeter Tyser /*
3ea0364f1SPeter Tyser * (C) Copyright 2002
4ea0364f1SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5ea0364f1SPeter Tyser */
6ea0364f1SPeter Tyser
7ea0364f1SPeter Tyser /* for now: just dummy functions to satisfy the linker */
8ea0364f1SPeter Tyser
9ea0364f1SPeter Tyser #include <common.h>
101dfdd9baSThierry Reding #include <malloc.h>
11ea0364f1SPeter Tyser
12633b6cceSWu, Josh /*
13633b6cceSWu, Josh * Flush range from all levels of d-cache/unified-cache.
14633b6cceSWu, Josh * Affects the range [start, start + size - 1].
15633b6cceSWu, Josh */
flush_cache(unsigned long start,unsigned long size)16fcfddfd5SJeroen Hofstee __weak void flush_cache(unsigned long start, unsigned long size)
17ea0364f1SPeter Tyser {
18633b6cceSWu, Josh flush_dcache_range(start, start + size);
19ea0364f1SPeter Tyser }
20e05f0079SAneesh V
21e05f0079SAneesh V /*
22e05f0079SAneesh V * Default implementation:
23e05f0079SAneesh V * do a range flush for the entire range
24e05f0079SAneesh V */
flush_dcache_all(void)25fcfddfd5SJeroen Hofstee __weak void flush_dcache_all(void)
26e05f0079SAneesh V {
27e05f0079SAneesh V flush_cache(0, ~0);
28e05f0079SAneesh V }
29cba4b180SAneesh V
30cba4b180SAneesh V /*
31cba4b180SAneesh V * Default implementation of enable_caches()
32cba4b180SAneesh V * Real implementation should be in platform code
33cba4b180SAneesh V */
enable_caches(void)34fcfddfd5SJeroen Hofstee __weak void enable_caches(void)
35cba4b180SAneesh V {
36cba4b180SAneesh V puts("WARNING: Caches not enabled\n");
37cba4b180SAneesh V }
381dfdd9baSThierry Reding
invalidate_dcache_range(unsigned long start,unsigned long stop)39387871a1SWu, Josh __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
40387871a1SWu, Josh {
41387871a1SWu, Josh /* An empty stub, real implementation should be in platform code */
42387871a1SWu, Josh }
flush_dcache_range(unsigned long start,unsigned long stop)43387871a1SWu, Josh __weak void flush_dcache_range(unsigned long start, unsigned long stop)
44387871a1SWu, Josh {
45387871a1SWu, Josh /* An empty stub, real implementation should be in platform code */
46387871a1SWu, Josh }
47387871a1SWu, Josh
check_cache_range(unsigned long start,unsigned long stop)48397b5697SSimon Glass int check_cache_range(unsigned long start, unsigned long stop)
49397b5697SSimon Glass {
50397b5697SSimon Glass int ok = 1;
51397b5697SSimon Glass
52397b5697SSimon Glass if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
53397b5697SSimon Glass ok = 0;
54397b5697SSimon Glass
55397b5697SSimon Glass if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
56397b5697SSimon Glass ok = 0;
57397b5697SSimon Glass
58397b5697SSimon Glass if (!ok) {
59bcc53bf0SSimon Glass warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
60397b5697SSimon Glass start, stop);
61397b5697SSimon Glass }
62397b5697SSimon Glass
63397b5697SSimon Glass return ok;
64397b5697SSimon Glass }
65397b5697SSimon Glass
661dfdd9baSThierry Reding #ifdef CONFIG_SYS_NONCACHED_MEMORY
671dfdd9baSThierry Reding /*
681dfdd9baSThierry Reding * Reserve one MMU section worth of address space below the malloc() area that
691dfdd9baSThierry Reding * will be mapped uncached.
701dfdd9baSThierry Reding */
711dfdd9baSThierry Reding static unsigned long noncached_start;
721dfdd9baSThierry Reding static unsigned long noncached_end;
731dfdd9baSThierry Reding static unsigned long noncached_next;
741dfdd9baSThierry Reding
noncached_init(void)751dfdd9baSThierry Reding void noncached_init(void)
761dfdd9baSThierry Reding {
771dfdd9baSThierry Reding phys_addr_t start, end;
781dfdd9baSThierry Reding size_t size;
791dfdd9baSThierry Reding
801dfdd9baSThierry Reding end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
811dfdd9baSThierry Reding size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
821dfdd9baSThierry Reding start = end - size;
831dfdd9baSThierry Reding
841dfdd9baSThierry Reding debug("mapping memory %pa-%pa non-cached\n", &start, &end);
851dfdd9baSThierry Reding
861dfdd9baSThierry Reding noncached_start = start;
871dfdd9baSThierry Reding noncached_end = end;
881dfdd9baSThierry Reding noncached_next = start;
891dfdd9baSThierry Reding
901dfdd9baSThierry Reding #ifndef CONFIG_SYS_DCACHE_OFF
911dfdd9baSThierry Reding mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
921dfdd9baSThierry Reding #endif
931dfdd9baSThierry Reding }
941dfdd9baSThierry Reding
noncached_alloc(size_t size,size_t align)951dfdd9baSThierry Reding phys_addr_t noncached_alloc(size_t size, size_t align)
961dfdd9baSThierry Reding {
971dfdd9baSThierry Reding phys_addr_t next = ALIGN(noncached_next, align);
981dfdd9baSThierry Reding
991dfdd9baSThierry Reding if (next >= noncached_end || (noncached_end - next) < size)
1001dfdd9baSThierry Reding return 0;
1011dfdd9baSThierry Reding
1021dfdd9baSThierry Reding debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
1031dfdd9baSThierry Reding noncached_next = next + size;
1041dfdd9baSThierry Reding
1051dfdd9baSThierry Reding return next;
1061dfdd9baSThierry Reding }
1071dfdd9baSThierry Reding #endif /* CONFIG_SYS_NONCACHED_MEMORY */
10862e92077SAlbert ARIBAUD
1093a649407STom Rini #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
invalidate_l2_cache(void)11062e92077SAlbert ARIBAUD void invalidate_l2_cache(void)
11162e92077SAlbert ARIBAUD {
11262e92077SAlbert ARIBAUD unsigned int val = 0;
11362e92077SAlbert ARIBAUD
11462e92077SAlbert ARIBAUD asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
11562e92077SAlbert ARIBAUD : : "r" (val) : "cc");
11662e92077SAlbert ARIBAUD isb();
11762e92077SAlbert ARIBAUD }
11862e92077SAlbert ARIBAUD #endif
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