Home
last modified time | relevance | path

Searched refs:intr_ctrl (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/hw/misc/
H A Daspeed_xdma.c88 if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) { in aspeed_xdma_write()
98 } else if (addr == axc->intr_ctrl) { in aspeed_xdma_write()
163 axc->intr_ctrl = XDMA_AST2600_IRQ_CTRL; in aspeed_2600_xdma_class_init()
186 axc->intr_ctrl = XDMA_IRQ_ENG_CTRL; in aspeed_2500_xdma_class_init()
208 axc->intr_ctrl = XDMA_IRQ_ENG_CTRL; in aspeed_2400_xdma_class_init()
/openbmc/qemu/include/hw/misc/
H A Daspeed_xdma.h40 uint8_t intr_ctrl; member
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c309 writel(BIT(31), &regs->intr_ctrl); in ast2500_sdrammc_ecc_enable()
310 writel(0, &regs->intr_ctrl); in ast2500_sdrammc_ecc_enable()
500 setbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL); in ast2500_sdrammc_probe()
510 clrbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL); in ast2500_sdrammc_probe()
H A Dsdram_ast2600.c786 writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl); in ast2600_sdrammc_common_init()
893 writel(BIT(31), &regs->intr_ctrl); in ast2600_sdrammc_ecc_enable()
894 writel(0, &regs->intr_ctrl); in ast2600_sdrammc_ecc_enable()
1019 clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR); in ast2600_sdrammc_probe()
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dsdram_ast2500.h118 u32 intr_ctrl; /* offset 0x50 */ member
H A Dsdram_ast2600.h150 u32 intr_ctrl; /* offset 0x50 */ member
H A Dscu_ast2400.h125 u32 intr_ctrl; /* 0x18 */ member
H A Dscu_ast2500.h129 u32 intr_ctrl; member
/openbmc/u-boot/drivers/spi/
H A Daspeed_spi.c25 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ member
379 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) in aspeed_spi_fmc_checksum()
382 writel(0x0, &priv->regs->intr_ctrl); in aspeed_spi_fmc_checksum()
419 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) in aspeed_g6_spi_fmc_checksum()
424 writel(0x0, &priv->regs->intr_ctrl); in aspeed_g6_spi_fmc_checksum()