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Searched refs:input_reg (Results 1 – 20 of 20) sorted by relevance

/openbmc/u-boot/drivers/pinctrl/nxp/
H A Dpinctrl-imx.c25 int mux_reg, conf_reg, input_reg; in imx_pinctrl_set_state() local
92 input_reg = pin_data[j++]; in imx_pinctrl_set_state()
100 mux_reg, conf_reg, input_reg, mux_mode, in imx_pinctrl_set_state()
149 val = readl(info->base + input_reg); in imx_pinctrl_set_state()
152 writel(val, info->base + input_reg); in imx_pinctrl_set_state()
153 } else if (input_reg) { in imx_pinctrl_set_state()
162 input_reg); in imx_pinctrl_set_state()
165 info->base + input_reg); in imx_pinctrl_set_state()
168 "0x%x\n", input_reg, input_val); in imx_pinctrl_set_state()
/openbmc/u-boot/drivers/gpio/
H A Dtca642x.c29 { .input_reg = 0x00,
33 { .input_reg = 0x01,
37 { .input_reg = 0x02,
133 uint8_t in_reg = tca642x_regs[gpio_bank].input_reg; in tca642x_get_val()
196 tca642x_regs[i].input_reg, &data) < 0) in tca642x_info()
/openbmc/u-boot/board/ti/omap5_uevm/
H A Devm.c48 { .input_reg = 0x00,
52 { .input_reg = 0x00,
56 { .input_reg = 0x00,
/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx.c220 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
223 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
224 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
231 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
234 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
237 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
490 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
H A Dpinctrl-imx.h31 u16 input_reg; member
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8ulp-pinctrl.yaml35 setting for one pin. The first 4 integers <mux_config_reg input_reg
46 "input_reg" indicates the offset of select input register.
H A Dfsl,imxrt1170.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
H A Dfsl,imx93-pinctrl.yaml38 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "input_reg" indicates the offset of select input register.
H A Dfsl,imxrt1050.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8m-pinctrl.yaml39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "input_reg" indicates the offset of select input register.
H A Dfsl,imx7d-pinctrl.yaml44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
57 "input_reg" indicates the offset of select input register.
H A Dfsl,imx6sx-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx6sll-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx6ul-pinctrl.txt10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx7ulp-pinctrl.txt17 <mux_conf_reg input_reg mux_mode input_val> are specified
H A Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/openbmc/u-boot/include/
H A Dtca642x.h54 uint8_t input_reg; member
/openbmc/qemu/hw/misc/
H A Dpca9552.c109 uint8_t input_reg = PCA9552_INPUT0 + (i / 8); in pca955x_update_pin_input() local
116 s->regs[input_reg] |= 1 << input_shift; in pca955x_update_pin_input()
120 s->regs[input_reg] &= ~(1 << input_shift); in pca955x_update_pin_input()
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-37xx.c1061 u32 mask, *irq_pol, input_reg, virq, type, level; in armada_3700_pinctrl_resume() local
1066 input_reg = INPUT_VAL; in armada_3700_pinctrl_resume()
1070 input_reg = INPUT_VAL + sizeof(u32); in armada_3700_pinctrl_resume()
1086 regmap_read(info->regmap, input_reg, &level); in armada_3700_pinctrl_resume()
/openbmc/linux/drivers/input/touchscreen/
H A Diqs5xx.c901 bool input_reg = !iqs5xx->input; in fw_file_store() local
925 if (input_reg) { in fw_file_store()