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Searched refs:imx_clk_hw_gate_dis (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8ulp.c206 clks[IMX8ULP_CLK_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("sosc_div1_gate", "sosc", base + 0x108, 7); in imx8ulp_clk_cgc1_init()
207 clks[IMX8ULP_CLK_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("sosc_div2_gate", "sosc", base + 0x108, 15); in imx8ulp_clk_cgc1_init()
208 clks[IMX8ULP_CLK_SOSC_DIV3_GATE] = imx_clk_hw_gate_dis("sosc_div3_gate", "sosc", base + 0x108, 23); in imx8ulp_clk_cgc1_init()
213 …clks[IMX8ULP_CLK_FROSC_DIV1_GATE] = imx_clk_hw_gate_dis("frosc_div1_gate", "frosc", base + 0x208, … in imx8ulp_clk_cgc1_init()
214 …clks[IMX8ULP_CLK_FROSC_DIV2_GATE] = imx_clk_hw_gate_dis("frosc_div2_gate", "frosc", base + 0x208, … in imx8ulp_clk_cgc1_init()
215 …clks[IMX8ULP_CLK_FROSC_DIV3_GATE] = imx_clk_hw_gate_dis("frosc_div3_gate", "frosc", base + 0x208, … in imx8ulp_clk_cgc1_init()
287 …clks[IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div1_gate", "sosc", base + … in imx8ulp_clk_cgc2_init()
288 …clks[IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div2_gate", "sosc", base + … in imx8ulp_clk_cgc2_init()
289 …clks[IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div3_gate", "sosc", base + … in imx8ulp_clk_cgc2_init()
294 …clks[IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE] = imx_clk_hw_gate_dis("cgc2_frosc_div1_gate", "frosc", base… in imx8ulp_clk_cgc2_init()
[all …]
H A Dclk-imx7d.c456 …hws[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m… in imx7d_clocks_init()
457 …hws[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m… in imx7d_clocks_init()
464 …hws[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m… in imx7d_clocks_init()
465 …hws[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m… in imx7d_clocks_init()
466 …hws[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m… in imx7d_clocks_init()
H A Dclk.h137 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
169 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ macro