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Searched refs:imm (Results 1 – 25 of 96) sorted by relevance

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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_shift.S5 .macro test_shift prefix, dst, src, v, imm argument
6 \prefix\()_set \dst, \src, \v, \imm
7 \prefix\()_ver \dst, \v, \imm
10 .macro test_shift_sd prefix, v, imm argument
11 test_shift \prefix, a3, a2, \v, \imm
12 test_shift \prefix, a2, a2, \v, \imm
32 .macro slli_set dst, src, v, imm argument
34 slli \dst, \src, \imm
37 .macro slli_ver dst, v, imm argument
39 movi a3, ((\v) << (\imm)) & 0xffffffff
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H A Dtest_sar.S5 .macro test_sar prefix, imm argument
6 \prefix\()_set \imm
7 \prefix\()_ver \imm
22 .macro sar_set imm argument
23 movi a2, \imm
27 .macro sar_ver imm argument
29 movi a2, \imm & 0x3f
37 .macro ssr_set imm argument
38 movi a2, \imm
42 .macro ssr_ver imm argument
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/openbmc/qemu/target/rx/
H A Dinsns.decode25 &ri rd imm
27 &rri rd imm rs2
29 &mi rs ld mi imm
44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8
45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0
46 @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0
47 @b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=%b2_r_0
48 @b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=%b2_li_8
50 @b2_ld_imm3 .... .. ld:2 rs:4 . imm:3 &mi mi=4
64 &rri rs2=%b3_r_0 imm=%b3_li_10
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H A Ddisas.c186 static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd) in prt_ir() argument
188 if (imm < 0x100) { in prt_ir()
189 prt("%s\t#%d, r%d", insn, imm, rd); in prt_ir()
191 prt("%s\t#0x%08x, r%d", insn, imm, rd); in prt_ir()
226 prt_ir(ctx, "mov.l", a->imm, a->rd); in trans_MOV_ir()
236 size[a->sz], a->imm, a->dsp << a->sz, a->rd); in trans_MOV_im()
239 size[a->sz], a->imm, a->rd); in trans_MOV_im()
414 prt_ir(ctx, "stz", a->imm, a->rd); in trans_STZ()
421 prt_ir(ctx, "stnz", a->imm, a->rd); in trans_STNZ()
428 prt("rtsd\t#%d", a->imm << 2); in trans_RTSD_i()
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/openbmc/qemu/target/riscv/
H A Dinsn16.decode57 &i imm rs1 rd !extern
58 &s imm rs1 rs2 !extern
59 &j imm rd !extern
60 &b imm rs2 rs1 !extern
61 &u imm rd !extern
71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3
73 @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
74 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
76 @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3
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/openbmc/qemu/target/avr/
H A Ddisas.c142 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
144 INSN(SUBI, "r%d, %d", a->rd, a->imm)
146 INSN(SBCI, "r%d, %d", a->rd, a->imm)
147 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
149 INSN(ANDI, "r%d, %d", a->rd, a->imm)
151 INSN(ORI, "r%d, %d", a->rd, a->imm)
163 INSN(DES, "%d", a->imm)
168 INSN(RJMP, ".%+d", a->imm * 2)
171 INSN(JMP, "0x%x", a->imm * 2)
172 INSN(RCALL, ".%+d", a->imm * 2)
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H A Dinsn.decode43 &rd_imm rd imm
46 @op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6
47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8
76 DES 1001 0100 imm:4 1011
88 @op_bit_imm .... .. imm:s7 bit:3
90 RJMP 1100 imm:s12
93 JMP 1001 010 ..... 110 . imm=%imm_call
94 RCALL 1101 imm:s12
97 CALL 1001 010 ..... 111 . imm=%imm_call
118 @io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm
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/openbmc/qemu/target/arm/tcg/
H A Dt16.decode25 &s_rri_rot !extern s rn rd imm rot
29 &ri !extern rd imm
31 &i !extern imm
33 &ldst_ri !extern p w u rn rt imm
37 &ci !extern cond imm
62 RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \
91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
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H A Dt32.decode25 &s_rri_rot !extern s rn rd imm rot
31 &ri !extern rd imm
33 &i !extern imm
39 &ldst_ri !extern p w u rn rt imm
41 &strex !extern rn rd rt rt2 imm
42 &ldrex !extern rn rt rt2 imm
45 &sat !extern rd rn satimm imm sh
46 &pkh !extern rd rn rm imm tb
148 &pkh imm=%imm5_12_6
172 &s_rri_rot imm=%t32extimm rot=%t32extrot
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H A Da32.decode28 &s_rri_rot s rn rd imm rot
34 &ri rd imm
36 &i imm
42 &ldst_ri p w u rn rt imm
44 &strex rn rd rt rt2 imm
45 &ldrex rn rt rt2 imm
48 &sat rd rn satimm imm sh
49 &pkh rd rn rm imm tb
80 @mov16 ---- .... .... .... rd:4 ............ &ri imm=%imm16
115 @s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \
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H A Dsve.decode72 &rri rd rn imm
74 &rrri rd rn rm imm
75 &rri_esz rd rn imm esz
76 &rrri_esz rd rn rm imm esz
86 &rpri_esz rd pg rn imm esz
88 &incdec_cnt rd pat esz imm d u
89 &incdec2_cnt rd rn pat esz imm d u
93 &rpri_load rd pg rn imm dtype nreg
95 &rpri_store rd pg rn imm msz esz nreg
97 &rpri_gather_load rd pg rn imm esz msz u ff
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H A Dvfp.decode83 VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp
84 VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
85 VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
95 VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
97 VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
100 VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
102 VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
158 vd=%vd_sp imm=%vmov_imm
160 vd=%vd_sp imm=%vmov_imm
162 vd=%vd_dp imm=%vmov_imm
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/openbmc/qemu/hw/mips/
H A Dbootloader.c104 bl_reg rs, bl_reg rt, uint16_t imm) in bl_gen_i_type() argument
112 insn = deposit32(insn, 0, 16, imm); in bl_gen_i_type()
159 static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) in bl_gen_lui() argument
162 bl_gen_i_type(p, 0x0f, 0, rt, imm); in bl_gen_lui()
178 static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) in bl_gen_ori() argument
180 bl_gen_i_type(p, 0x0d, rs, rt, imm); in bl_gen_ori()
216 static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) in bl_gen_li() argument
219 bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); in bl_gen_li()
220 bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); in bl_gen_li()
222 bl_gen_lui(p, rt, extract32(imm, 16, 16)); in bl_gen_li()
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/openbmc/qemu/tests/qemu-iotests/
H A D026.out.nocache6 Event: l1_update; errno: 5; imm: off; once: on; write
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
16 Event: l1_update; errno: 5; imm: off; once: off; write
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
30 Event: l1_update; errno: 28; imm: off; once: on; write
35 Event: l1_update; errno: 28; imm: off; once: on; write -b
40 Event: l1_update; errno: 28; imm: off; once: off; write
47 Event: l1_update; errno: 28; imm: off; once: off; write -b
54 Event: l2_load; errno: 5; imm: off; once: on; write
62 Event: l2_load; errno: 5; imm: off; once: on; write -b
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H A D026.out6 Event: l1_update; errno: 5; imm: off; once: on; write
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
16 Event: l1_update; errno: 5; imm: off; once: off; write
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
30 Event: l1_update; errno: 28; imm: off; once: on; write
35 Event: l1_update; errno: 28; imm: off; once: on; write -b
40 Event: l1_update; errno: 28; imm: off; once: off; write
47 Event: l1_update; errno: 28; imm: off; once: off; write -b
54 Event: l2_load; errno: 5; imm: off; once: on; write
62 Event: l2_load; errno: 5; imm: off; once: on; write -b
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H A D02684 for imm in off; do
92 immediately = "$imm"
99 echo "Event: $event; errno: $errno; imm: $imm; once: $once; write $vmstate"
142 for imm in off; do
150 immediately = "$imm"
157 echo "Event: $event; errno: $errno; imm: $imm; once: $once; write $vmstate"
182 for imm in off; do
189 immediately = "$imm"
196 echo "Event: $event; errno: $errno; imm: $imm; once: $once"
/openbmc/qemu/target/microblaze/
H A Dinsns.decode24 &typeb rd ra imm
25 &typeb_br rd imm
26 &typeb_bc ra imm
27 &type_msr rd imm
33 @typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm
45 @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb
48 @typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm
51 @typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=%extimm
54 # them back together as "imm". Doing this makes it easiest to
57 @typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm
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/openbmc/qemu/target/hexagon/
H A Dgen_trans_funcs.py52 imm = immre.findall(hex_common.semdict[tag])
53 if len(imm) == 0:
56 letter = re.split("\\(", imm[0])[1]
113 for imm in imms:
114 imm_type = imm[0]
117 imm_shift = int(imm[2]) if imm[2] else 0
H A Dgen_decodetree.py149 for imm in imms:
150 immno = 1 if imm[0].isupper() else 0
151 imm_type = imm[0]
152 imm_width = int(imm[1])
179 for imm in imms:
180 imm_type = imm[0]
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-daemons/opensaf/opensaf/
H A D0001-immpbe_dump.cc-Use-sys-wait.h-instead-of-wait.h.patch14 src/imm/common/immpbe_dump.cc | 2 +-
17 diff --git a/src/imm/common/immpbe_dump.cc b/src/imm/common/immpbe_dump.cc
19 --- a/src/imm/common/immpbe_dump.cc
20 +++ b/src/imm/common/immpbe_dump.cc
H A D0001-include-cstdint-for-uintXX_t-types.patch13 src/imm/immnd/ImmModel.h | 1 +
17 diff --git a/src/imm/immnd/ImmModel.h b/src/imm/immnd/ImmModel.h
19 --- a/src/imm/immnd/ImmModel.h
20 +++ b/src/imm/immnd/ImmModel.h
/openbmc/u-boot/drivers/bios_emulator/x86emu/
H A Dops.c926 u32 imm; in x86emuOp_push_word_IMM() local
930 imm = fetch_long_imm(); in x86emuOp_push_word_IMM()
932 imm = fetch_word_imm(); in x86emuOp_push_word_IMM()
934 DECODE_PRINTF2("PUSH\t%x\n", imm); in x86emuOp_push_word_IMM()
937 push_long(imm); in x86emuOp_push_word_IMM()
939 push_word((u16)imm); in x86emuOp_push_word_IMM()
963 s32 imm; in x86emuOp_imul_word_IMM() local
968 imm = fetch_long_imm(); in x86emuOp_imul_word_IMM()
969 DECODE_PRINTF2(",%d\n", (s32)imm); in x86emuOp_imul_word_IMM()
971 imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); in x86emuOp_imul_word_IMM()
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/openbmc/qemu/target/loongarch/
H A Dinsns.decode20 &i imm
21 &r_i rd imm
25 &rr_i rd rj imm
26 &hint_r_i hint rj imm
44 &fr_i fd rj imm
52 &i_rr imm rj rk
53 &cop_r_i cop rj imm
54 &j_i rj imm
59 @i15 .... ........ ..... imm:15 &i
63 @r_i20 .... ... imm:s20 rd:5 &r_i
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/openbmc/qemu/target/mips/tcg/
H A Dmips16e_translate.c.inc458 int16_t imm, offset;
466 offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11
476 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
479 gen_addiupc(ctx, rx, imm, 0, 1);
522 imm = ctx->opcode & 0xf;
523 imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4;
524 imm = imm | ((ctx->opcode >> 16) & 0xf) << 11;
525 imm = (int16_t) (imm << 1) >> 1;
529 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
534 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
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/openbmc/qemu/target/loongarch/tcg/
H A Dvec_helper.c406 void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
415 Vd->E(i) = DO_OP(Vj->E(i), (TD)imm); \
916 void HELPER(vnori_b)(void *vd, void *vj, uint64_t imm, uint32_t desc) in HELPER()
923 Vd->B(i) = ~(Vj->B(i) | (uint8_t)imm); in HELPER()
928 void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
940 temp.E1(j + ofs * i) = (TD)Vj->E2(j + ofs * 2 * i) << (imm % BIT); \
1013 void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
1021 Vd->E(i) = do_vsrlr_ ## E(Vj->E(i), imm); \
1065 void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
1073 Vd->E(i) = do_vsrar_ ## E(Vj->E(i), imm); \
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