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Searched refs:hws_access_type (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_prv_if.h25 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
28 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
44 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
47 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
48 enum hws_access_type phy_access_type, u32 phy_id,
51 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
56 u32 dev_num, enum hws_access_type access_type, u32 if_id,
74 u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type,
100 int (*mv_ddr_phy_read)(enum hws_access_type phy_access,
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H A Dddr3_training_ip_flow.h67 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
69 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
72 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
75 enum hws_access_type access_type,
79 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
82 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
83 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
86 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
103 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
107 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
H A Dddr3_training_ip_engine.h43 enum hws_access_type pup_access_type,
52 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
54 enum hws_access_type pup_access_type,
63 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
65 enum hws_access_type pup_access_type,
83 int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern,
H A Dddr3_training_bist.c13 enum hws_access_type access_type,
21 enum hws_access_type access_type, u32 if_num, in ddr3_tip_bist_activate()
168 enum hws_access_type access_type, in ddr3_tip_bist_operation()
423 static int mv_ddr_bist_tx(enum hws_access_type access_type) in mv_ddr_bist_tx()
441 static int mv_ddr_odpg_bist_prepare(enum hws_pattern pattern, enum hws_access_type access_type, in mv_ddr_odpg_bist_prepare()
H A Dddr3_training_ip_engine.c336 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_ip_training()
338 enum hws_access_type pup_access_type, in ddr3_tip_ip_training()
571 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_load_pattern_to_odpg()
625 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_configure_odpg()
693 enum hws_access_type pup_access_type, in ddr3_tip_read_training_result()
956 enum hws_access_type access_type, in ddr3_tip_ip_training_wrapper_int()
958 enum hws_access_type pup_access_type, in ddr3_tip_ip_training_wrapper_int()
1094 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_ip_training_wrapper()
1096 enum hws_access_type pup_access_type, in ddr3_tip_ip_training_wrapper()
1643 int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern, in mv_ddr_load_dm_pattern_to_odpg()
H A Dddr3_training.c93 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
101 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
103 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
346 enum hws_access_type access_type = ACCESS_TYPE_UNICAST; in hws_ddr3_tip_init_controller()
991 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_if_write()
1002 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_if_read()
1013 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_if_polling()
1066 enum hws_access_type phy_access, u32 phy_id, in ddr3_tip_bus_read()
1077 u32 if_id, enum hws_access_type phy_access, in ddr3_tip_bus_write()
1123 int adll_calibration(u32 dev_num, enum hws_access_type access_type, in adll_calibration()
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H A Dddr3_training_ip_bist.h38 enum hws_access_type access_type,
H A Dddr3_training_ip.h85 enum hws_access_type { enum
H A Dmv_ddr_plat.c591 static int prfa_write(enum hws_access_type phy_access, u32 phy, in prfa_write()
614 static int prfa_read(enum hws_access_type phy_access, u32 phy, in prfa_read()
H A Dddr3_training_hw_algo.c51 enum hws_access_type access_type = ACCESS_TYPE_UNICAST; in ddr3_tip_write_additional_odt_setting()
H A Dddr3_debug.c952 enum hws_access_type pup_access; in ddr3_tip_run_sweep_test()
1099 enum hws_access_type pup_access; in ddr3_tip_run_leveling_sweep_test()