183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_BIST_H_ 7f1df9364SStefan Roese #define _DDR3_TRAINING_IP_BIST_H_ 8f1df9364SStefan Roese 9f1df9364SStefan Roese #include "ddr3_training_ip.h" 10f1df9364SStefan Roese 11f1df9364SStefan Roese enum hws_bist_operation { 12f1df9364SStefan Roese BIST_STOP = 0, 13f1df9364SStefan Roese BIST_START = 1 14f1df9364SStefan Roese }; 15f1df9364SStefan Roese 16f1df9364SStefan Roese enum hws_stress_jump { 17f1df9364SStefan Roese STRESS_NONE = 0, 18f1df9364SStefan Roese STRESS_ENABLE = 1 19f1df9364SStefan Roese }; 20f1df9364SStefan Roese 21f1df9364SStefan Roese enum hws_pattern_duration { 22f1df9364SStefan Roese DURATION_SINGLE = 0, 23f1df9364SStefan Roese DURATION_STOP_AT_FAIL = 1, 24f1df9364SStefan Roese DURATION_ADDRESS = 2, 25f1df9364SStefan Roese DURATION_CONT = 4 26f1df9364SStefan Roese }; 27f1df9364SStefan Roese 28f1df9364SStefan Roese struct bist_result { 29f1df9364SStefan Roese u32 bist_error_cnt; 30f1df9364SStefan Roese u32 bist_fail_low; 31f1df9364SStefan Roese u32 bist_fail_high; 32f1df9364SStefan Roese u32 bist_last_fail_addr; 33f1df9364SStefan Roese }; 34f1df9364SStefan Roese 35f1df9364SStefan Roese int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, 36f1df9364SStefan Roese struct bist_result *pst_bist_result); 37f1df9364SStefan Roese int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, 38f1df9364SStefan Roese enum hws_access_type access_type, 39f1df9364SStefan Roese u32 if_num, enum hws_dir direction, 40f1df9364SStefan Roese enum hws_stress_jump addr_stress_jump, 41f1df9364SStefan Roese enum hws_pattern_duration duration, 42f1df9364SStefan Roese enum hws_bist_operation oper_type, 43f1df9364SStefan Roese u32 offset, u32 cs_num, u32 pattern_addr_length); 44f1df9364SStefan Roese int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, 45f1df9364SStefan Roese u32 cs_num); 46f1df9364SStefan Roese int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, 47f1df9364SStefan Roese u32 mode); 48*2b4ffbf6SChris Packham int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num, 49*2b4ffbf6SChris Packham u32 direction, u32 mode); 50f1df9364SStefan Roese int ddr3_tip_print_regs(u32 dev_num); 51f1df9364SStefan Roese int ddr3_tip_reg_dump(u32 dev_num); 52f1df9364SStefan Roese int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type, 53f1df9364SStefan Roese u32 burst_length); 54*2b4ffbf6SChris Packham int mv_ddr_dm_to_dq_diff_get(u8 adll_byte_high, u8 adll_byte_low, u8 *vw_vector, 55*2b4ffbf6SChris Packham int *delta_h_adll, int *delta_l_adll); 56*2b4ffbf6SChris Packham int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector); 57f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_BIST_H_ */ 58