Searched refs:gur_in32 (Results 1 – 14 of 14) sorted by relevance
36 #define gur_in32(a) in_le32(a) macro38 #define gur_in32(a) in_be32(a) macro54 val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; in fsl_check_boot_mode_secure()61 val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; in fsl_check_boot_mode_secure()
128 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in esdhc_dspi_status_fixup()147 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) in esdhc_dspi_status_fixup()164 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in esdhc_dspi_status_fixup()332 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in config_board_mux()354 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) in config_board_mux()371 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in config_board_mux()
87 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()90 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()95 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
92 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in serdes_get_first_lane()99 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); in serdes_get_first_lane()106 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); in serdes_get_first_lane()142 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; in serdes_init()397 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in setup_serdes_volt()401 u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); in setup_serdes_volt()406 u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); in setup_serdes_volt()
42 u32 cfg = gur_in32(&gur->rcwsr[4]); in serdes_get_first_lane()78 u32 cfg = gur_in32(&gur->rcwsr[4]) & in get_serdes_protocol()111 cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()148 u32 cfg_rcw4 = gur_in32(&gur->rcwsr[4]); in setup_serdes_volt()149 u32 cfg_rcw5 = gur_in32(&gur->rcwsr[5]); in setup_serdes_volt()
368 svr = gur_in32(&gur->svr); in cpu_name()432 svr = gur_in32(&gur->svr); in fix_pcie_mmu_map()836 type = gur_in32(&gur->tp_ityp[idx]); in initiator_type()852 cluster = gur_in32(&gur->tp_cluster[i].lower); in cpu_pos_mask()873 cluster = gur_in32(&gur->tp_cluster[i].lower); in cpu_mask()906 cluster = gur_in32(&gur->tp_cluster[i].lower); in fsl_qoriq_core_to_cluster()930 cluster = gur_in32(&gur->tp_cluster[i].lower); in fsl_qoriq_core_to_type()950 return gur_in32(&gur->svr); in get_svr()961 u32 type, rcw, svr = gur_in32(&gur->svr); in print_cpuinfo()1002 rcw = gur_in32(&gur->rcwsr[i]); in print_cpuinfo()
65 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()72 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
174 val = gur_in32(&gur->svr); in fdt_fixup_gic()356 rev = gur_in32(&gur->svr); in fdt_fixup_msi()407 unsigned int svr = gur_in32(&gur->svr); in ft_cpu_setup()
62 while (gur_in32(&gur->scratchrw[6]) != 0) in wake_secondary_core_n()103 svr = gur_in32(&gur->svr); in fsl_layerscape_wake_seconday_cores()
35 u32 svr = gur_in32(&gur->svr); in soc_has_dp_ddr()49 u32 svr = gur_in32(&gur->svr); in soc_has_aiop()383 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); in erratum_a009929()
96 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR]) in fsl_rgmii_init()105 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR]) in fsl_rgmii_init()
90 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) in fsl_rgmii_init()99 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) in fsl_rgmii_init()
21 #define gur_in32(a) in_le32(a) macro24 #define gur_in32(a) in_be32(a) macro
254 u32 svr = gur_in32(&gur->svr); in misc_init_r()