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Searched refs:grf (Results 1 – 25 of 64) sorted by relevance

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/openbmc/u-boot/drivers/net/
H A Dgmac_rockchip.c77 struct rk322x_grf *grf; in rk3228_gmac_fix_mac_speed() local
102 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3228_gmac_fix_mac_speed()
103 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); in rk3228_gmac_fix_mac_speed()
110 struct rk3288_grf *grf; in rk3288_gmac_fix_mac_speed() local
128 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3288_gmac_fix_mac_speed()
129 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); in rk3288_gmac_fix_mac_speed()
136 struct rk3328_grf_regs *grf; in rk3328_gmac_fix_mac_speed() local
161 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3328_gmac_fix_mac_speed()
162 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); in rk3328_gmac_fix_mac_speed()
169 struct rk3368_grf *grf; in rk3368_gmac_fix_mac_speed() local
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3288_mipi.c32 struct rk3288_grf *grf = priv->grf; in rk_mipi_dsi_source_select() local
38 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
43 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
59 struct rk3288_grf *grf = priv->grf; in rk_mipi_dphy_mode_set() local
64 rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
69 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
75 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
135 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk_mipi_ofdata_to_platdata()
136 if (IS_ERR_OR_NULL(priv->grf)) { in rk_mipi_ofdata_to_platdata()
138 __func__, priv->grf); in rk_mipi_ofdata_to_platdata()
H A Drk3399_mipi.c30 struct rk3399_grf_regs *grf = priv->grf; in rk_mipi_dsi_source_select() local
36 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
40 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
55 struct rk3399_grf_regs *grf = priv->grf; in rk_mipi_dphy_mode_set() local
60 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
64 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); in rk_mipi_dphy_mode_set()
68 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); in rk_mipi_dphy_mode_set()
127 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk_mipi_ofdata_to_platdata()
128 if (IS_ERR_OR_NULL(priv->grf)) { in rk_mipi_ofdata_to_platdata()
130 __func__, priv->grf); in rk_mipi_ofdata_to_platdata()
H A Drk3288_hdmi.c28 struct rk3288_grf *grf = priv->grf; in rk3288_hdmi_enable() local
31 rk_setreg(&grf->soc_con6, 1 << 15); in rk3288_hdmi_enable()
34 rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); in rk3288_hdmi_enable()
H A Drk3399_hdmi.c28 struct rk3399_grf_regs *grf = priv->grf; in rk3399_hdmi_enable() local
31 rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK, in rk3399_hdmi_enable()
/openbmc/u-boot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c68 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in mcu_init() local
71 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
73 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
75 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
77 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
79 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, in mcu_init()
81 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, in mcu_init()
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3188-board.c27 struct rk3188_grf *grf; in board_late_init() local
30 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in board_late_init()
31 if (IS_ERR(grf)) { in board_late_init()
32 pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); in board_late_init()
35 rk_clrsetreg(&grf->soc_con0, in board_late_init()
H A Drk3399-board-spl.c135 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; in board_debug_uart_init() local
143 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
146 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
151 rk_setreg(&grf->io_vsel, 1 << 0); in board_debug_uart_init()
165 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
168 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
172 rk_clrsetreg(&grf->soc_con7, in board_debug_uart_init()
183 struct rk3399_grf_regs *grf; in board_init_f() local
235 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in board_init_f()
236 rk_clrreg(&grf->emmccore_con[11], 0x0ff); in board_init_f()
H A Drk322x-board.c35 struct rk322x_grf * const grf = (void *)GRF_BASE; in board_init() local
55 rk_clrsetreg(&grf->gpio1b_iomux, in board_init()
60 rk_clrsetreg(&grf->con_iomux, in board_init()
68 rk_clrsetreg(&grf->macphy_con[0], in board_init()
145 struct rk322x_grf *grf; in fastboot_set_reboot_flag() local
148 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in fastboot_set_reboot_flag()
150 writel(BOOT_FASTBOOT, &grf->os_reg[0]); in fastboot_set_reboot_flag()
H A Drk3188-board-spl.c100 struct rk3188_grf * const grf = (void *)GRF_BASE; in board_debug_uart_init() local
114 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
141 rk_clrsetreg(&grf->uoc0_con[0], in board_init_f()
145 rk_clrsetreg(&grf->uoc0_con[2], in board_init_f()
147 rk_clrsetreg(&grf->uoc0_con[3], in board_init_f()
154 rk_clrsetreg(&grf->uoc0_con[0], in board_init_f()
H A Drk322x-board-spl.c30 static struct rk322x_grf * const grf = (void *)GRF_BASE; in board_debug_uart_init() local
52 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
57 rk_clrsetreg(&grf->con_iomux, in board_debug_uart_init()
H A Drk3128-board.c117 struct rk3128_grf *grf; in fastboot_set_reboot_flag() local
120 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in fastboot_set_reboot_flag()
122 writel(BOOT_FASTBOOT, &grf->os_reg[0]); in fastboot_set_reboot_flag()
H A Drk3036-board-spl.c23 struct rk3036_grf * const grf = (void *)GRF_BASE; in board_init_f() local
29 rk_clrsetreg(&grf->gpio1c_iomux, in board_init_f()
H A Drk3368-board-tpl.c89 struct rk3368_grf * const grf = in board_debug_uart_init() local
104 rk_clrsetreg(&grf->gpio2d_iomux, in board_debug_uart_init()
106 rk_clrsetreg(&grf->gpio2d_iomux, in board_debug_uart_init()
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A Devb_rv1108.c18 struct rv1108_grf *grf; in mach_cpu_init() local
38 grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); in mach_cpu_init()
41 rk_clrsetreg(&grf->gpio2d_iomux, in mach_cpu_init()
45 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); in mach_cpu_init()
/openbmc/u-boot/board/elgin/elgin_rv1108/
H A Delgin_rv1108.c19 struct rv1108_grf *grf; in mach_cpu_init() local
39 grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); in mach_cpu_init()
42 rk_clrsetreg(&grf->gpio2d_iomux, in mach_cpu_init()
46 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); in mach_cpu_init()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3328.c16 struct rk3328_grf_regs *grf; member
23 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3328_dmc_probe()
24 debug("%s: grf=%p\n", __func__, priv->grf); in rk3328_dmc_probe()
27 (phys_addr_t)&priv->grf->os_reg[2]); in rk3328_dmc_probe()
H A Dsdram_rk3128.c16 struct rk3128_grf *grf; member
23 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3128_dmc_probe()
24 debug("%s: grf=%p\n", __func__, priv->grf); in rk3128_dmc_probe()
27 (phys_addr_t)&priv->grf->os_reg[1]); in rk3128_dmc_probe()
H A Dsdram_rk3188.c38 struct rk3188_grf *grf; member
197 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) in ddr_set_enable() argument
204 rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); in ddr_set_enable()
207 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, in ddr_set_ddr3_mode() argument
214 rk_clrsetreg(&grf->soc_con2, mask, val); in ddr_set_ddr3_mode()
217 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable) in ddr_rank_2_row15en() argument
223 rk_clrsetreg(&grf->soc_con2, mask, val); in ddr_rank_2_row15en()
228 struct rk3188_grf *grf) in pctl_cfg() argument
247 ddr_set_ddr3_mode(grf, channel, true); in pctl_cfg()
248 ddr_set_enable(grf, channel, true); in pctl_cfg()
[all …]
H A Ddmc-rk3368.c26 struct rk3368_grf *grf; member
138 static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable) in ddr_set_noc_spr_err_stall() argument
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
146 static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode) in ddr_set_ddr3_mode() argument
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
546 struct rk3368_grf *grf) in pctl_cfg() argument
564 writel(0x001c0004, &grf->ddrc0_con0); in pctl_cfg()
801 struct rk3368_grf *grf = priv->grf; in setup_sdram() local
[all …]
H A Dsdram_rk3288.c40 struct rk3288_grf *grf; member
196 static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable) in ddr_set_enable() argument
204 rk_clrsetreg(&grf->soc_con0, in ddr_set_enable()
209 static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel, in ddr_set_ddr3_mode() argument
217 rk_clrsetreg(&grf->soc_con0, mask, val); in ddr_set_ddr3_mode()
220 static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel, in ddr_set_en_bst_odt() argument
231 rk_clrsetreg(&grf->soc_con2, mask, in ddr_set_en_bst_odt()
241 struct rk3288_grf *grf) in pctl_cfg() argument
260 ddr_set_ddr3_mode(grf, channel, false); in pctl_cfg()
261 ddr_set_enable(grf, channel, true); in pctl_cfg()
[all …]
H A Dsdram_rk322x.c37 struct rk322x_grf *grf; member
366 struct rk322x_grf *grf = dram->grf; in phy_softreset() local
368 writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); in phy_softreset()
374 writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); in phy_softreset()
382 struct rk322x_grf *grf = dram->grf; in set_bw() local
387 writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]); in set_bw()
394 &grf->soc_con[0]); in set_bw()
402 struct rk322x_grf *grf) in pctl_cfg() argument
436 writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); in pctl_cfg()
463 writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); in pctl_cfg()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi177 rockchip,grf = <&grf>;
223 grf: grf@20008000 { label
233 rockchip,grf = <&grf>;
250 rockchip,grf = <&grf>;
265 rockchip,grf = <&grf>;
320 rockchip,grf = <&grf>;
335 rockchip,grf = <&grf>;
350 rockchip,grf = <&grf>;
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3188.c119 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_ddr() argument
155 while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) in rkclk_configure_ddr()
165 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_cpu() argument
204 while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) in rkclk_configure_cpu()
372 static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_init() argument
389 while ((readl(&grf->soc_status0) & in rkclk_init()
503 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
507 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
552 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3188_clk_probe()
553 if (IS_ERR(priv->grf)) in rk3188_clk_probe()
[all …]
H A Dclk_rk3328.c404 struct rk3328_grf_regs *grf; in rk3328_gmac2io_set_clk() local
407 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3328_gmac2io_set_clk()
413 if (readl(&grf->mac_con[1]) & BIT(10) && in rk3328_gmac2io_set_clk()
414 readl(&grf->soc_con[4]) & BIT(14)) { in rk3328_gmac2io_set_clk()
656 struct rk3328_grf_regs *grf; in rk3328_gmac2io_set_parent() local
660 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3328_gmac2io_set_parent()
668 rk_clrreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
684 rk_setreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
693 struct rk3328_grf_regs *grf; in rk3328_gmac2io_ext_set_parent() local
697 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3328_gmac2io_ext_set_parent()
[all …]

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