Searched refs:gb_addr_config_fields (Results 1 – 7 of 7) sorted by relevance
218 adev->gfx.config.gb_addr_config_fields.num_pipes; in fill_gfx9_tiling_info_from_device()220 adev->gfx.config.gb_addr_config_fields.num_banks; in fill_gfx9_tiling_info_from_device()222 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; in fill_gfx9_tiling_info_from_device()224 adev->gfx.config.gb_addr_config_fields.num_se; in fill_gfx9_tiling_info_from_device()226 adev->gfx.config.gb_addr_config_fields.max_compress_frags; in fill_gfx9_tiling_info_from_device()228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; in fill_gfx9_tiling_info_from_device()231 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in fill_gfx9_tiling_info_from_device()361 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in add_gfx10_1_modifiers()406 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in add_gfx9_modifiers()408 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in add_gfx9_modifiers()[all …]
728 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in convert_tiling_flags_to_modifier()729 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; in convert_tiling_flags_to_modifier()803 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); in convert_tiling_flags_to_modifier()808 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); in convert_tiling_flags_to_modifier()814 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()815 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in convert_tiling_flags_to_modifier()817 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()819 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in convert_tiling_flags_to_modifier()
220 struct gb_addr_config gb_addr_config_fields; member
701 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_4_3_gpu_early_init()708 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_4_3_gpu_early_init()710 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_4_3_gpu_early_init()715 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_4_3_gpu_early_init()720 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_4_3_gpu_early_init()725 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_4_3_gpu_early_init()730 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_4_3_gpu_early_init()
4221 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()4226 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()4231 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()4233 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()4236 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()4239 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()4242 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
1931 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()1938 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()1940 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()1945 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()1950 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()1955 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()1960 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
4381 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()4400 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()4405 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()4407 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()4410 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()4413 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()4416 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()