1d38ceaf9SAlex Deucher /*
2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc.
3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc.
4d38ceaf9SAlex Deucher *
5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a
6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"),
7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation
8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the
10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions:
11d38ceaf9SAlex Deucher *
12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in
13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software.
14d38ceaf9SAlex Deucher *
15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE.
22d38ceaf9SAlex Deucher *
23d38ceaf9SAlex Deucher * Authors: Dave Airlie
24d38ceaf9SAlex Deucher * Alex Deucher
25d38ceaf9SAlex Deucher */
26fdf2f6c5SSam Ravnborg
27d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h>
28d38ceaf9SAlex Deucher #include "amdgpu.h"
29d38ceaf9SAlex Deucher #include "amdgpu_i2c.h"
30d38ceaf9SAlex Deucher #include "atom.h"
31d38ceaf9SAlex Deucher #include "amdgpu_connectors.h"
325d43be0cSChristian König #include "amdgpu_display.h"
33543036a2SAurabindo Pillai #include "soc15_common.h"
34543036a2SAurabindo Pillai #include "gc/gc_11_0_0_offset.h"
35543036a2SAurabindo Pillai #include "gc/gc_11_0_0_sh_mask.h"
36d38ceaf9SAlex Deucher #include <asm/div64.h>
37d38ceaf9SAlex Deucher
38fdf2f6c5SSam Ravnborg #include <linux/pci.h>
39d38ceaf9SAlex Deucher #include <linux/pm_runtime.h>
40d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h>
410a611560SHamza Mahfooz #include <drm/drm_damage_helper.h>
420a611560SHamza Mahfooz #include <drm/drm_drv.h>
43d38ceaf9SAlex Deucher #include <drm/drm_edid.h>
44ab77e02cSNoralf Trønnes #include <drm/drm_fb_helper.h>
4545b64fd9SThomas Zimmermann #include <drm/drm_gem_framebuffer_helper.h>
4608d76915SBas Nieuwenhuizen #include <drm/drm_fourcc.h>
47973ad627SThomas Zimmermann #include <drm/drm_modeset_helper.h>
48fdf2f6c5SSam Ravnborg #include <drm/drm_vblank.h>
49d38ceaf9SAlex Deucher
50a347ca97SAlex Deucher /**
51a347ca97SAlex Deucher * amdgpu_display_hotplug_work_func - work handler for display hotplug event
52a347ca97SAlex Deucher *
53a347ca97SAlex Deucher * @work: work struct pointer
54a347ca97SAlex Deucher *
55a347ca97SAlex Deucher * This is the hotplug event work handler (all ASICs).
56a347ca97SAlex Deucher * The work gets scheduled from the IRQ handler if there
57a347ca97SAlex Deucher * was a hotplug interrupt. It walks through the connector table
58a347ca97SAlex Deucher * and calls hotplug handler for each connector. After this, it sends
59a347ca97SAlex Deucher * a DRM hotplug event to alert userspace.
60a347ca97SAlex Deucher *
61a347ca97SAlex Deucher * This design approach is required in order to defer hotplug event handling
62a347ca97SAlex Deucher * from the IRQ handler to a work handler because hotplug handler has to use
63a347ca97SAlex Deucher * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
64a347ca97SAlex Deucher * sleep).
65a347ca97SAlex Deucher */
amdgpu_display_hotplug_work_func(struct work_struct * work)66a347ca97SAlex Deucher void amdgpu_display_hotplug_work_func(struct work_struct *work)
67a347ca97SAlex Deucher {
68a347ca97SAlex Deucher struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
6990f56611Sxurui hotplug_work.work);
70a347ca97SAlex Deucher struct drm_device *dev = adev_to_drm(adev);
71a347ca97SAlex Deucher struct drm_mode_config *mode_config = &dev->mode_config;
72a347ca97SAlex Deucher struct drm_connector *connector;
73a347ca97SAlex Deucher struct drm_connector_list_iter iter;
74a347ca97SAlex Deucher
75a347ca97SAlex Deucher mutex_lock(&mode_config->mutex);
76a347ca97SAlex Deucher drm_connector_list_iter_begin(dev, &iter);
77a347ca97SAlex Deucher drm_for_each_connector_iter(connector, &iter)
78a347ca97SAlex Deucher amdgpu_connector_hotplug(connector);
79a347ca97SAlex Deucher drm_connector_list_iter_end(&iter);
80a347ca97SAlex Deucher mutex_unlock(&mode_config->mutex);
81a347ca97SAlex Deucher /* Just fire off a uevent and let userspace tell us what to do */
82a347ca97SAlex Deucher drm_helper_hpd_irq_event(dev);
83a347ca97SAlex Deucher }
84a347ca97SAlex Deucher
8531d5c523SAlex Deucher static int amdgpu_display_framebuffer_init(struct drm_device *dev,
8631d5c523SAlex Deucher struct amdgpu_framebuffer *rfb,
8731d5c523SAlex Deucher const struct drm_mode_fb_cmd2 *mode_cmd,
8831d5c523SAlex Deucher struct drm_gem_object *obj);
8931d5c523SAlex Deucher
amdgpu_display_flip_callback(struct dma_fence * f,struct dma_fence_cb * cb)903a05dc00SSamuel Li static void amdgpu_display_flip_callback(struct dma_fence *f,
913a05dc00SSamuel Li struct dma_fence_cb *cb)
92c3874b75SChristian König {
93c3874b75SChristian König struct amdgpu_flip_work *work =
94c3874b75SChristian König container_of(cb, struct amdgpu_flip_work, cb);
95c3874b75SChristian König
96f54d1867SChris Wilson dma_fence_put(f);
97325cbba1SMichel Dänzer schedule_work(&work->flip_work.work);
98c3874b75SChristian König }
99c3874b75SChristian König
amdgpu_display_flip_handle_fence(struct amdgpu_flip_work * work,struct dma_fence ** f)1003a05dc00SSamuel Li static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
101f54d1867SChris Wilson struct dma_fence **f)
1021ffd2652SChristian König {
103f54d1867SChris Wilson struct dma_fence *fence = *f;
1041ffd2652SChristian König
105c3874b75SChristian König if (fence == NULL)
106c3874b75SChristian König return false;
1071ffd2652SChristian König
1081ffd2652SChristian König *f = NULL;
109c3874b75SChristian König
1103a05dc00SSamuel Li if (!dma_fence_add_callback(fence, &work->cb,
1113a05dc00SSamuel Li amdgpu_display_flip_callback))
112c3874b75SChristian König return true;
113c3874b75SChristian König
114f54d1867SChris Wilson dma_fence_put(fence);
115c3874b75SChristian König return false;
1161ffd2652SChristian König }
117d38ceaf9SAlex Deucher
amdgpu_display_flip_work_func(struct work_struct * __work)1183a05dc00SSamuel Li static void amdgpu_display_flip_work_func(struct work_struct *__work)
119d38ceaf9SAlex Deucher {
120325cbba1SMichel Dänzer struct delayed_work *delayed_work =
121325cbba1SMichel Dänzer container_of(__work, struct delayed_work, work);
122d38ceaf9SAlex Deucher struct amdgpu_flip_work *work =
123325cbba1SMichel Dänzer container_of(delayed_work, struct amdgpu_flip_work, flip_work);
124d38ceaf9SAlex Deucher struct amdgpu_device *adev = work->adev;
125f93932bcSAlex Deucher struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
126d38ceaf9SAlex Deucher
127f93932bcSAlex Deucher struct drm_crtc *crtc = &amdgpu_crtc->base;
128d38ceaf9SAlex Deucher unsigned long flags;
12993125cb7SSrinivasan Shanmugam unsigned int i;
130325cbba1SMichel Dänzer int vpos, hpos;
131d38ceaf9SAlex Deucher
1321ffd2652SChristian König for (i = 0; i < work->shared_count; ++i)
1333a05dc00SSamuel Li if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
134c3874b75SChristian König return;
135d38ceaf9SAlex Deucher
136325cbba1SMichel Dänzer /* Wait until we're out of the vertical blank period before the one
137325cbba1SMichel Dänzer * targeted by the flip
138325cbba1SMichel Dänzer */
139f93932bcSAlex Deucher if (amdgpu_crtc->enabled &&
1404a580877SLuben Tuikov (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
141325cbba1SMichel Dänzer &vpos, &hpos, NULL, NULL,
142325cbba1SMichel Dänzer &crtc->hwmode)
143325cbba1SMichel Dänzer & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
144325cbba1SMichel Dänzer (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
145325cbba1SMichel Dänzer (int)(work->target_vblank -
146e3eff4b5SThomas Zimmermann amdgpu_get_vblank_counter_kms(crtc)) > 0) {
147325cbba1SMichel Dänzer schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
148325cbba1SMichel Dänzer return;
149325cbba1SMichel Dänzer }
150325cbba1SMichel Dänzer
151d38ceaf9SAlex Deucher /* We borrow the event spin lock for protecting flip_status */
152d38ceaf9SAlex Deucher spin_lock_irqsave(&crtc->dev->event_lock, flags);
153d38ceaf9SAlex Deucher
154bd4c72d1SAndrey Grodzovsky /* Do the flip (mmio) */
155cb9e59d7SAlex Deucher adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
156bd4c72d1SAndrey Grodzovsky
157bd4c72d1SAndrey Grodzovsky /* Set the flip status */
158f93932bcSAlex Deucher amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
159d38ceaf9SAlex Deucher spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1606bd9e877SVitaly Prosyak
161bd4c72d1SAndrey Grodzovsky
1629f07550bSSean Paul drm_dbg_vbl(adev_to_drm(adev),
1639f07550bSSean Paul "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
164f93932bcSAlex Deucher amdgpu_crtc->crtc_id, amdgpu_crtc, work);
165bd4c72d1SAndrey Grodzovsky
166d38ceaf9SAlex Deucher }
167d38ceaf9SAlex Deucher
168d38ceaf9SAlex Deucher /*
169d38ceaf9SAlex Deucher * Handle unpin events outside the interrupt handler proper.
170d38ceaf9SAlex Deucher */
amdgpu_display_unpin_work_func(struct work_struct * __work)1713a05dc00SSamuel Li static void amdgpu_display_unpin_work_func(struct work_struct *__work)
172d38ceaf9SAlex Deucher {
173d38ceaf9SAlex Deucher struct amdgpu_flip_work *work =
174d38ceaf9SAlex Deucher container_of(__work, struct amdgpu_flip_work, unpin_work);
175d38ceaf9SAlex Deucher int r;
176d38ceaf9SAlex Deucher
177d38ceaf9SAlex Deucher /* unpin of the old buffer */
178c81a1a74SMichel Dänzer r = amdgpu_bo_reserve(work->old_abo, true);
179d38ceaf9SAlex Deucher if (likely(r == 0)) {
1804671078eSChristian König amdgpu_bo_unpin(work->old_abo);
181765e7fbfSChristian König amdgpu_bo_unreserve(work->old_abo);
182d38ceaf9SAlex Deucher } else
183d38ceaf9SAlex Deucher DRM_ERROR("failed to reserve buffer after flip\n");
184d38ceaf9SAlex Deucher
185765e7fbfSChristian König amdgpu_bo_unref(&work->old_abo);
1861ffd2652SChristian König kfree(work->shared);
187d38ceaf9SAlex Deucher kfree(work);
188d38ceaf9SAlex Deucher }
189d38ceaf9SAlex Deucher
amdgpu_display_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)1900cd11932SSamuel Li int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
191d38ceaf9SAlex Deucher struct drm_framebuffer *fb,
192d38ceaf9SAlex Deucher struct drm_pending_vblank_event *event,
1935f42aa39SHarry Wentland uint32_t page_flip_flags, uint32_t target,
1945f42aa39SHarry Wentland struct drm_modeset_acquire_ctx *ctx)
195d38ceaf9SAlex Deucher {
196d38ceaf9SAlex Deucher struct drm_device *dev = crtc->dev;
1971348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
198d38ceaf9SAlex Deucher struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
199d38ceaf9SAlex Deucher struct drm_gem_object *obj;
200d38ceaf9SAlex Deucher struct amdgpu_flip_work *work;
201765e7fbfSChristian König struct amdgpu_bo *new_abo;
202d38ceaf9SAlex Deucher unsigned long flags;
203d38ceaf9SAlex Deucher u64 tiling_flags;
2045f42aa39SHarry Wentland int i, r;
205d38ceaf9SAlex Deucher
20693125cb7SSrinivasan Shanmugam work = kzalloc(sizeof(*work), GFP_KERNEL);
207d38ceaf9SAlex Deucher if (work == NULL)
208d38ceaf9SAlex Deucher return -ENOMEM;
209d38ceaf9SAlex Deucher
2103a05dc00SSamuel Li INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
2113a05dc00SSamuel Li INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
212d38ceaf9SAlex Deucher
213d38ceaf9SAlex Deucher work->event = event;
214d38ceaf9SAlex Deucher work->adev = adev;
215d38ceaf9SAlex Deucher work->crtc_id = amdgpu_crtc->crtc_id;
216cb9e59d7SAlex Deucher work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
217d38ceaf9SAlex Deucher
218d38ceaf9SAlex Deucher /* schedule unpin of the old buffer */
219e68d14ddSDaniel Stone obj = crtc->primary->fb->obj[0];
220d38ceaf9SAlex Deucher
221d38ceaf9SAlex Deucher /* take a reference to the old object */
222765e7fbfSChristian König work->old_abo = gem_to_amdgpu_bo(obj);
223765e7fbfSChristian König amdgpu_bo_ref(work->old_abo);
224d38ceaf9SAlex Deucher
225e68d14ddSDaniel Stone obj = fb->obj[0];
226765e7fbfSChristian König new_abo = gem_to_amdgpu_bo(obj);
227d38ceaf9SAlex Deucher
228d38ceaf9SAlex Deucher /* pin the new buffer */
229765e7fbfSChristian König r = amdgpu_bo_reserve(new_abo, false);
230d38ceaf9SAlex Deucher if (unlikely(r != 0)) {
231765e7fbfSChristian König DRM_ERROR("failed to reserve new abo buffer before flip\n");
232d38ceaf9SAlex Deucher goto cleanup;
233d38ceaf9SAlex Deucher }
234d38ceaf9SAlex Deucher
23547bbcc1eSEmily Deng if (!adev->enable_virtual_display) {
236f2bd8a0eSAndrey Grodzovsky r = amdgpu_bo_pin(new_abo,
237f2bd8a0eSAndrey Grodzovsky amdgpu_display_supported_domains(adev, new_abo->flags));
238d38ceaf9SAlex Deucher if (unlikely(r != 0)) {
239765e7fbfSChristian König DRM_ERROR("failed to pin new abo buffer before flip\n");
240ee7fd957SMichel Dänzer goto unreserve;
241d38ceaf9SAlex Deucher }
24247bbcc1eSEmily Deng }
243d38ceaf9SAlex Deucher
244bb812f1eSJunwei Zhang r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
245bb812f1eSJunwei Zhang if (unlikely(r != 0)) {
246bb812f1eSJunwei Zhang DRM_ERROR("%p bind failed\n", new_abo);
247bb812f1eSJunwei Zhang goto unpin;
248bb812f1eSJunwei Zhang }
249bb812f1eSJunwei Zhang
2507bc80a54SChristian König r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
25175ab2b36SChristian König &work->shared_count,
25275ab2b36SChristian König &work->shared);
2531ffd2652SChristian König if (unlikely(r != 0)) {
2541ffd2652SChristian König DRM_ERROR("failed to get fences for buffer\n");
255ee7fd957SMichel Dänzer goto unpin;
2561ffd2652SChristian König }
2571ffd2652SChristian König
258765e7fbfSChristian König amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
259765e7fbfSChristian König amdgpu_bo_unreserve(new_abo);
260d38ceaf9SAlex Deucher
26147bbcc1eSEmily Deng if (!adev->enable_virtual_display)
2627b7c6c81SJunwei Zhang work->base = amdgpu_bo_gpu_offset(new_abo);
26323effc11SDhinakaran Pandiyan work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
264e3eff4b5SThomas Zimmermann amdgpu_get_vblank_counter_kms(crtc);
265d38ceaf9SAlex Deucher
266d38ceaf9SAlex Deucher /* we borrow the event spin lock for protecting flip_wrok */
267d38ceaf9SAlex Deucher spin_lock_irqsave(&crtc->dev->event_lock, flags);
268d38ceaf9SAlex Deucher if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
269d38ceaf9SAlex Deucher DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
270d38ceaf9SAlex Deucher spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
271d38ceaf9SAlex Deucher r = -EBUSY;
272325cbba1SMichel Dänzer goto pflip_cleanup;
2739c5b2b0dSHarry Wentland }
2749c5b2b0dSHarry Wentland
2759c5b2b0dSHarry Wentland amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
2769c5b2b0dSHarry Wentland amdgpu_crtc->pflip_works = work;
2779c5b2b0dSHarry Wentland
2785f42aa39SHarry Wentland
2795f42aa39SHarry Wentland DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
2805f42aa39SHarry Wentland amdgpu_crtc->crtc_id, amdgpu_crtc, work);
2819c5b2b0dSHarry Wentland /* update crtc fb */
2829c5b2b0dSHarry Wentland crtc->primary->fb = fb;
2839c5b2b0dSHarry Wentland spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2843a05dc00SSamuel Li amdgpu_display_flip_work_func(&work->flip_work.work);
2859c5b2b0dSHarry Wentland return 0;
2865f42aa39SHarry Wentland
2875f42aa39SHarry Wentland pflip_cleanup:
2885f42aa39SHarry Wentland if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
2895f42aa39SHarry Wentland DRM_ERROR("failed to reserve new abo in error path\n");
2905f42aa39SHarry Wentland goto cleanup;
2915f42aa39SHarry Wentland }
2925f42aa39SHarry Wentland unpin:
29347bbcc1eSEmily Deng if (!adev->enable_virtual_display)
2944671078eSChristian König amdgpu_bo_unpin(new_abo);
29547bbcc1eSEmily Deng
2965f42aa39SHarry Wentland unreserve:
2975f42aa39SHarry Wentland amdgpu_bo_unreserve(new_abo);
2985f42aa39SHarry Wentland
2995f42aa39SHarry Wentland cleanup:
3005f42aa39SHarry Wentland amdgpu_bo_unref(&work->old_abo);
3015f42aa39SHarry Wentland for (i = 0; i < work->shared_count; ++i)
3025f42aa39SHarry Wentland dma_fence_put(work->shared[i]);
3035f42aa39SHarry Wentland kfree(work->shared);
3045f42aa39SHarry Wentland kfree(work);
3055f42aa39SHarry Wentland
3065f42aa39SHarry Wentland return r;
307d38ceaf9SAlex Deucher }
308d38ceaf9SAlex Deucher
amdgpu_display_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)309775a8364SSamuel Li int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
310a4eff9aaSDaniel Vetter struct drm_modeset_acquire_ctx *ctx)
311d38ceaf9SAlex Deucher {
312d38ceaf9SAlex Deucher struct drm_device *dev;
313d38ceaf9SAlex Deucher struct amdgpu_device *adev;
314d38ceaf9SAlex Deucher struct drm_crtc *crtc;
315d38ceaf9SAlex Deucher bool active = false;
316d38ceaf9SAlex Deucher int ret;
317d38ceaf9SAlex Deucher
318d38ceaf9SAlex Deucher if (!set || !set->crtc)
319d38ceaf9SAlex Deucher return -EINVAL;
320d38ceaf9SAlex Deucher
321d38ceaf9SAlex Deucher dev = set->crtc->dev;
322d38ceaf9SAlex Deucher
323d38ceaf9SAlex Deucher ret = pm_runtime_get_sync(dev->dev);
324d38ceaf9SAlex Deucher if (ret < 0)
325e008fa6fSNavid Emamdoost goto out;
326d38ceaf9SAlex Deucher
327a4eff9aaSDaniel Vetter ret = drm_crtc_helper_set_config(set, ctx);
328d38ceaf9SAlex Deucher
329d38ceaf9SAlex Deucher list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
330d38ceaf9SAlex Deucher if (crtc->enabled)
331d38ceaf9SAlex Deucher active = true;
332d38ceaf9SAlex Deucher
333d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(dev->dev);
334d38ceaf9SAlex Deucher
3351348969aSLuben Tuikov adev = drm_to_adev(dev);
336d38ceaf9SAlex Deucher /* if we have active crtcs and we don't have a power ref,
33793125cb7SSrinivasan Shanmugam * take the current one
33893125cb7SSrinivasan Shanmugam */
339d38ceaf9SAlex Deucher if (active && !adev->have_disp_power_ref) {
340d38ceaf9SAlex Deucher adev->have_disp_power_ref = true;
3413514521cSJean Delvare return ret;
342d38ceaf9SAlex Deucher }
343*f6f4be2cSPrike Liang /* if we have no active crtcs, then go to
344*f6f4be2cSPrike Liang * drop the power ref we got before
34593125cb7SSrinivasan Shanmugam */
346*f6f4be2cSPrike Liang if (!active && adev->have_disp_power_ref)
347d38ceaf9SAlex Deucher adev->have_disp_power_ref = false;
348e008fa6fSNavid Emamdoost out:
349d38ceaf9SAlex Deucher /* drop the power reference we got coming in here */
350d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(dev->dev);
351d38ceaf9SAlex Deucher return ret;
352d38ceaf9SAlex Deucher }
353d38ceaf9SAlex Deucher
354c6e14f40SEmily Deng static const char *encoder_names[41] = {
355d38ceaf9SAlex Deucher "NONE",
356d38ceaf9SAlex Deucher "INTERNAL_LVDS",
357d38ceaf9SAlex Deucher "INTERNAL_TMDS1",
358d38ceaf9SAlex Deucher "INTERNAL_TMDS2",
359d38ceaf9SAlex Deucher "INTERNAL_DAC1",
360d38ceaf9SAlex Deucher "INTERNAL_DAC2",
361d38ceaf9SAlex Deucher "INTERNAL_SDVOA",
362d38ceaf9SAlex Deucher "INTERNAL_SDVOB",
363d38ceaf9SAlex Deucher "SI170B",
364d38ceaf9SAlex Deucher "CH7303",
365d38ceaf9SAlex Deucher "CH7301",
366d38ceaf9SAlex Deucher "INTERNAL_DVO1",
367d38ceaf9SAlex Deucher "EXTERNAL_SDVOA",
368d38ceaf9SAlex Deucher "EXTERNAL_SDVOB",
369d38ceaf9SAlex Deucher "TITFP513",
370d38ceaf9SAlex Deucher "INTERNAL_LVTM1",
371d38ceaf9SAlex Deucher "VT1623",
372d38ceaf9SAlex Deucher "HDMI_SI1930",
373d38ceaf9SAlex Deucher "HDMI_INTERNAL",
374d38ceaf9SAlex Deucher "INTERNAL_KLDSCP_TMDS1",
375d38ceaf9SAlex Deucher "INTERNAL_KLDSCP_DVO1",
376d38ceaf9SAlex Deucher "INTERNAL_KLDSCP_DAC1",
377d38ceaf9SAlex Deucher "INTERNAL_KLDSCP_DAC2",
378d38ceaf9SAlex Deucher "SI178",
379d38ceaf9SAlex Deucher "MVPU_FPGA",
380d38ceaf9SAlex Deucher "INTERNAL_DDI",
381d38ceaf9SAlex Deucher "VT1625",
382d38ceaf9SAlex Deucher "HDMI_SI1932",
383d38ceaf9SAlex Deucher "DP_AN9801",
384d38ceaf9SAlex Deucher "DP_DP501",
385d38ceaf9SAlex Deucher "INTERNAL_UNIPHY",
386d38ceaf9SAlex Deucher "INTERNAL_KLDSCP_LVTMA",
387d38ceaf9SAlex Deucher "INTERNAL_UNIPHY1",
388d38ceaf9SAlex Deucher "INTERNAL_UNIPHY2",
389d38ceaf9SAlex Deucher "NUTMEG",
390d38ceaf9SAlex Deucher "TRAVIS",
391d38ceaf9SAlex Deucher "INTERNAL_VCE",
392d38ceaf9SAlex Deucher "INTERNAL_UNIPHY3",
393c6e14f40SEmily Deng "HDMI_ANX9805",
394c6e14f40SEmily Deng "INTERNAL_AMCLK",
395c6e14f40SEmily Deng "VIRTUAL",
396d38ceaf9SAlex Deucher };
397d38ceaf9SAlex Deucher
398d38ceaf9SAlex Deucher static const char *hpd_names[6] = {
399d38ceaf9SAlex Deucher "HPD1",
400d38ceaf9SAlex Deucher "HPD2",
401d38ceaf9SAlex Deucher "HPD3",
402d38ceaf9SAlex Deucher "HPD4",
403d38ceaf9SAlex Deucher "HPD5",
404d38ceaf9SAlex Deucher "HPD6",
405d38ceaf9SAlex Deucher };
406d38ceaf9SAlex Deucher
amdgpu_display_print_display_setup(struct drm_device * dev)40750af9193SSamuel Li void amdgpu_display_print_display_setup(struct drm_device *dev)
408d38ceaf9SAlex Deucher {
409d38ceaf9SAlex Deucher struct drm_connector *connector;
410d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector;
411d38ceaf9SAlex Deucher struct drm_encoder *encoder;
412d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
413f8d2d39eSLyude Paul struct drm_connector_list_iter iter;
414d38ceaf9SAlex Deucher uint32_t devices;
415d38ceaf9SAlex Deucher int i = 0;
416d38ceaf9SAlex Deucher
417f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter);
418d38ceaf9SAlex Deucher DRM_INFO("AMDGPU Display Connectors\n");
419f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) {
420d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector);
421d38ceaf9SAlex Deucher DRM_INFO("Connector %d:\n", i);
422d38ceaf9SAlex Deucher DRM_INFO(" %s\n", connector->name);
423d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
424d38ceaf9SAlex Deucher DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
425d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) {
426d38ceaf9SAlex Deucher DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
427d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.mask_clk_reg,
428d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.mask_data_reg,
429d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.a_clk_reg,
430d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.a_data_reg,
431d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.en_clk_reg,
432d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.en_data_reg,
433d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.y_clk_reg,
434d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.y_data_reg);
435d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid)
436d38ceaf9SAlex Deucher DRM_INFO(" DDC Router 0x%x/0x%x\n",
437d38ceaf9SAlex Deucher amdgpu_connector->router.ddc_mux_control_pin,
438d38ceaf9SAlex Deucher amdgpu_connector->router.ddc_mux_state);
439d38ceaf9SAlex Deucher if (amdgpu_connector->router.cd_valid)
440d38ceaf9SAlex Deucher DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
441d38ceaf9SAlex Deucher amdgpu_connector->router.cd_mux_control_pin,
442d38ceaf9SAlex Deucher amdgpu_connector->router.cd_mux_state);
443d38ceaf9SAlex Deucher } else {
444d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
445d38ceaf9SAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
446d38ceaf9SAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
447d38ceaf9SAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
448d38ceaf9SAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
449d38ceaf9SAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
450d38ceaf9SAlex Deucher DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
451d38ceaf9SAlex Deucher }
452d38ceaf9SAlex Deucher DRM_INFO(" Encoders:\n");
453d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
454d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
455d38ceaf9SAlex Deucher devices = amdgpu_encoder->devices & amdgpu_connector->devices;
456d38ceaf9SAlex Deucher if (devices) {
457d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_CRT1_SUPPORT)
458d38ceaf9SAlex Deucher DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
459d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_CRT2_SUPPORT)
460d38ceaf9SAlex Deucher DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
461d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_LCD1_SUPPORT)
462d38ceaf9SAlex Deucher DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
463d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_DFP1_SUPPORT)
464d38ceaf9SAlex Deucher DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
465d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_DFP2_SUPPORT)
466d38ceaf9SAlex Deucher DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
467d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_DFP3_SUPPORT)
468d38ceaf9SAlex Deucher DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
469d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_DFP4_SUPPORT)
470d38ceaf9SAlex Deucher DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
471d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_DFP5_SUPPORT)
472d38ceaf9SAlex Deucher DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
473d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_DFP6_SUPPORT)
474d38ceaf9SAlex Deucher DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
475d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_TV1_SUPPORT)
476d38ceaf9SAlex Deucher DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
477d38ceaf9SAlex Deucher if (devices & ATOM_DEVICE_CV_SUPPORT)
478d38ceaf9SAlex Deucher DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
479d38ceaf9SAlex Deucher }
480d38ceaf9SAlex Deucher }
481d38ceaf9SAlex Deucher i++;
482d38ceaf9SAlex Deucher }
483f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter);
484d38ceaf9SAlex Deucher }
485d38ceaf9SAlex Deucher
amdgpu_display_ddc_probe(struct amdgpu_connector * amdgpu_connector,bool use_aux)486e0b5b5ecSSamuel Li bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
487d38ceaf9SAlex Deucher bool use_aux)
488d38ceaf9SAlex Deucher {
489d38ceaf9SAlex Deucher u8 out = 0x0;
490d38ceaf9SAlex Deucher u8 buf[8];
491d38ceaf9SAlex Deucher int ret;
492d38ceaf9SAlex Deucher struct i2c_msg msgs[] = {
493d38ceaf9SAlex Deucher {
494d38ceaf9SAlex Deucher .addr = DDC_ADDR,
495d38ceaf9SAlex Deucher .flags = 0,
496d38ceaf9SAlex Deucher .len = 1,
497d38ceaf9SAlex Deucher .buf = &out,
498d38ceaf9SAlex Deucher },
499d38ceaf9SAlex Deucher {
500d38ceaf9SAlex Deucher .addr = DDC_ADDR,
501d38ceaf9SAlex Deucher .flags = I2C_M_RD,
502d38ceaf9SAlex Deucher .len = 8,
503d38ceaf9SAlex Deucher .buf = buf,
504d38ceaf9SAlex Deucher }
505d38ceaf9SAlex Deucher };
506d38ceaf9SAlex Deucher
507d38ceaf9SAlex Deucher /* on hw with routers, select right port */
508d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid)
509d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
510d38ceaf9SAlex Deucher
51193125cb7SSrinivasan Shanmugam if (use_aux)
512d38ceaf9SAlex Deucher ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
51393125cb7SSrinivasan Shanmugam else
514d38ceaf9SAlex Deucher ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
515d38ceaf9SAlex Deucher
516d38ceaf9SAlex Deucher if (ret != 2)
517d38ceaf9SAlex Deucher /* Couldn't find an accessible DDC on this connector */
518d38ceaf9SAlex Deucher return false;
519d38ceaf9SAlex Deucher /* Probe also for valid EDID header
520d38ceaf9SAlex Deucher * EDID header starts with:
521d38ceaf9SAlex Deucher * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
522d38ceaf9SAlex Deucher * Only the first 6 bytes must be valid as
52393125cb7SSrinivasan Shanmugam * drm_edid_block_valid() can fix the last 2 bytes
52493125cb7SSrinivasan Shanmugam */
525d38ceaf9SAlex Deucher if (drm_edid_header_is_valid(buf) < 6) {
526d38ceaf9SAlex Deucher /* Couldn't find an accessible EDID on this
52793125cb7SSrinivasan Shanmugam * connector
52893125cb7SSrinivasan Shanmugam */
529d38ceaf9SAlex Deucher return false;
530d38ceaf9SAlex Deucher }
531d38ceaf9SAlex Deucher return true;
532d38ceaf9SAlex Deucher }
533d38ceaf9SAlex Deucher
amdgpu_dirtyfb(struct drm_framebuffer * fb,struct drm_file * file,unsigned int flags,unsigned int color,struct drm_clip_rect * clips,unsigned int num_clips)5340a611560SHamza Mahfooz static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file,
5350a611560SHamza Mahfooz unsigned int flags, unsigned int color,
5360a611560SHamza Mahfooz struct drm_clip_rect *clips, unsigned int num_clips)
5370a611560SHamza Mahfooz {
5380a611560SHamza Mahfooz
5390a611560SHamza Mahfooz if (file)
5400a611560SHamza Mahfooz return -ENOSYS;
5410a611560SHamza Mahfooz
5420a611560SHamza Mahfooz return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
5430a611560SHamza Mahfooz num_clips);
5440a611560SHamza Mahfooz }
5450a611560SHamza Mahfooz
546d38ceaf9SAlex Deucher static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
547e68d14ddSDaniel Stone .destroy = drm_gem_fb_destroy,
548e68d14ddSDaniel Stone .create_handle = drm_gem_fb_create_handle,
549e9127f5eSAlex Deucher };
550e9127f5eSAlex Deucher
5510a611560SHamza Mahfooz static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
5520a611560SHamza Mahfooz .destroy = drm_gem_fb_destroy,
5530a611560SHamza Mahfooz .create_handle = drm_gem_fb_create_handle,
5540a611560SHamza Mahfooz .dirty = amdgpu_dirtyfb
5550a611560SHamza Mahfooz };
5560a611560SHamza Mahfooz
amdgpu_display_supported_domains(struct amdgpu_device * adev,uint64_t bo_flags)557f2bd8a0eSAndrey Grodzovsky uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
558f2bd8a0eSAndrey Grodzovsky uint64_t bo_flags)
5595d43be0cSChristian König {
5605d43be0cSChristian König uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
5615d43be0cSChristian König
5622c9c178bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC)
563ddcb7fc6SAndrey Grodzovsky /*
564f2bd8a0eSAndrey Grodzovsky * if amdgpu_bo_support_uswc returns false it means that USWC mappings
565ddcb7fc6SAndrey Grodzovsky * is not supported for this board. But this mapping is required
566ddcb7fc6SAndrey Grodzovsky * to avoid hang caused by placement of scanout BO in GTT on certain
567ddcb7fc6SAndrey Grodzovsky * APUs. So force the BO placement to VRAM in case this architecture
568ddcb7fc6SAndrey Grodzovsky * will not allow USWC mappings.
569f4d4f53fSBhaskar Chowdhury * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
570ddcb7fc6SAndrey Grodzovsky */
571403c1ef0SAlex Deucher if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
572f2bd8a0eSAndrey Grodzovsky amdgpu_bo_support_uswc(bo_flags) &&
573d09ef243SAlex Deucher adev->dc_enabled &&
574a7f520bfSAlex Deucher adev->mode_info.gpu_vm_support)
5755d43be0cSChristian König domain |= AMDGPU_GEM_DOMAIN_GTT;
5762c9c178bSAlex Deucher #endif
5775d43be0cSChristian König
5785d43be0cSChristian König return domain;
5795d43be0cSChristian König }
5805d43be0cSChristian König
581816853f9SBas Nieuwenhuizen static const struct drm_format_info dcc_formats[] = {
582816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
583816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
584816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
585816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
586816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
587816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
588816853f9SBas Nieuwenhuizen .has_alpha = true, },
589816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
590816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
591816853f9SBas Nieuwenhuizen .has_alpha = true, },
592816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
593816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
594816853f9SBas Nieuwenhuizen .has_alpha = true, },
595816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
596816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
597816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
598816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
599816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
600816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
601816853f9SBas Nieuwenhuizen .has_alpha = true, },
602816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
603816853f9SBas Nieuwenhuizen .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
604816853f9SBas Nieuwenhuizen .has_alpha = true, },
605816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
606816853f9SBas Nieuwenhuizen .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
607816853f9SBas Nieuwenhuizen };
608816853f9SBas Nieuwenhuizen
609816853f9SBas Nieuwenhuizen static const struct drm_format_info dcc_retile_formats[] = {
610816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
611816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
612816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
613816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
614816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
615816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
616816853f9SBas Nieuwenhuizen .has_alpha = true, },
617816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
618816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
619816853f9SBas Nieuwenhuizen .has_alpha = true, },
620816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
621816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
622816853f9SBas Nieuwenhuizen .has_alpha = true, },
623816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
624816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
625816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
626816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
627816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
628816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
629816853f9SBas Nieuwenhuizen .has_alpha = true, },
630816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
631816853f9SBas Nieuwenhuizen .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
632816853f9SBas Nieuwenhuizen .has_alpha = true, },
633816853f9SBas Nieuwenhuizen { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
634816853f9SBas Nieuwenhuizen .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
635816853f9SBas Nieuwenhuizen };
636816853f9SBas Nieuwenhuizen
637816853f9SBas Nieuwenhuizen static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],int num_formats,u32 format)638816853f9SBas Nieuwenhuizen lookup_format_info(const struct drm_format_info formats[],
639816853f9SBas Nieuwenhuizen int num_formats, u32 format)
640816853f9SBas Nieuwenhuizen {
641816853f9SBas Nieuwenhuizen int i;
642816853f9SBas Nieuwenhuizen
643816853f9SBas Nieuwenhuizen for (i = 0; i < num_formats; i++) {
644816853f9SBas Nieuwenhuizen if (formats[i].format == format)
645816853f9SBas Nieuwenhuizen return &formats[i];
646816853f9SBas Nieuwenhuizen }
647816853f9SBas Nieuwenhuizen
648816853f9SBas Nieuwenhuizen return NULL;
649816853f9SBas Nieuwenhuizen }
650816853f9SBas Nieuwenhuizen
651816853f9SBas Nieuwenhuizen const struct drm_format_info *
amdgpu_lookup_format_info(u32 format,uint64_t modifier)652816853f9SBas Nieuwenhuizen amdgpu_lookup_format_info(u32 format, uint64_t modifier)
653816853f9SBas Nieuwenhuizen {
654816853f9SBas Nieuwenhuizen if (!IS_AMD_FMT_MOD(modifier))
655816853f9SBas Nieuwenhuizen return NULL;
656816853f9SBas Nieuwenhuizen
657816853f9SBas Nieuwenhuizen if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
658816853f9SBas Nieuwenhuizen return lookup_format_info(dcc_retile_formats,
659816853f9SBas Nieuwenhuizen ARRAY_SIZE(dcc_retile_formats),
660816853f9SBas Nieuwenhuizen format);
661816853f9SBas Nieuwenhuizen
662816853f9SBas Nieuwenhuizen if (AMD_FMT_MOD_GET(DCC, modifier))
663816853f9SBas Nieuwenhuizen return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
664816853f9SBas Nieuwenhuizen format);
665816853f9SBas Nieuwenhuizen
666816853f9SBas Nieuwenhuizen /* returning NULL will cause the default format structs to be used. */
667816853f9SBas Nieuwenhuizen return NULL;
668816853f9SBas Nieuwenhuizen }
669816853f9SBas Nieuwenhuizen
6701331e630SBas Nieuwenhuizen
6711331e630SBas Nieuwenhuizen /*
6721331e630SBas Nieuwenhuizen * Tries to extract the renderable DCC offset from the opaque metadata attached
6731331e630SBas Nieuwenhuizen * to the buffer.
6741331e630SBas Nieuwenhuizen */
6751331e630SBas Nieuwenhuizen static int
extract_render_dcc_offset(struct amdgpu_device * adev,struct drm_gem_object * obj,uint64_t * offset)6761331e630SBas Nieuwenhuizen extract_render_dcc_offset(struct amdgpu_device *adev,
6771331e630SBas Nieuwenhuizen struct drm_gem_object *obj,
6781331e630SBas Nieuwenhuizen uint64_t *offset)
6791331e630SBas Nieuwenhuizen {
6801331e630SBas Nieuwenhuizen struct amdgpu_bo *rbo;
6811331e630SBas Nieuwenhuizen int r = 0;
6821331e630SBas Nieuwenhuizen uint32_t metadata[10]; /* Something that fits a descriptor + header. */
6831331e630SBas Nieuwenhuizen uint32_t size;
6841331e630SBas Nieuwenhuizen
6851331e630SBas Nieuwenhuizen rbo = gem_to_amdgpu_bo(obj);
6861331e630SBas Nieuwenhuizen r = amdgpu_bo_reserve(rbo, false);
6871331e630SBas Nieuwenhuizen
6881331e630SBas Nieuwenhuizen if (unlikely(r)) {
6891331e630SBas Nieuwenhuizen /* Don't show error message when returning -ERESTARTSYS */
6901331e630SBas Nieuwenhuizen if (r != -ERESTARTSYS)
6911331e630SBas Nieuwenhuizen DRM_ERROR("Unable to reserve buffer: %d\n", r);
6921331e630SBas Nieuwenhuizen return r;
6931331e630SBas Nieuwenhuizen }
6941331e630SBas Nieuwenhuizen
6951331e630SBas Nieuwenhuizen r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
6961331e630SBas Nieuwenhuizen amdgpu_bo_unreserve(rbo);
6971331e630SBas Nieuwenhuizen
6981331e630SBas Nieuwenhuizen if (r)
6991331e630SBas Nieuwenhuizen return r;
7001331e630SBas Nieuwenhuizen
7011331e630SBas Nieuwenhuizen /*
7021331e630SBas Nieuwenhuizen * The first word is the metadata version, and we need space for at least
7031331e630SBas Nieuwenhuizen * the version + pci vendor+device id + 8 words for a descriptor.
7041331e630SBas Nieuwenhuizen */
7051331e630SBas Nieuwenhuizen if (size < 40 || metadata[0] != 1)
7061331e630SBas Nieuwenhuizen return -EINVAL;
7071331e630SBas Nieuwenhuizen
7081331e630SBas Nieuwenhuizen if (adev->family >= AMDGPU_FAMILY_NV) {
7091331e630SBas Nieuwenhuizen /* resource word 6/7 META_DATA_ADDRESS{_LO} */
7101331e630SBas Nieuwenhuizen *offset = ((u64)metadata[9] << 16u) |
7111331e630SBas Nieuwenhuizen ((metadata[8] & 0xFF000000u) >> 16);
7121331e630SBas Nieuwenhuizen } else {
7131331e630SBas Nieuwenhuizen /* resource word 5/7 META_DATA_ADDRESS */
7141331e630SBas Nieuwenhuizen *offset = ((u64)metadata[9] << 8u) |
7151331e630SBas Nieuwenhuizen ((u64)(metadata[7] & 0x1FE0000u) << 23);
7161331e630SBas Nieuwenhuizen }
7171331e630SBas Nieuwenhuizen
7181331e630SBas Nieuwenhuizen return 0;
7191331e630SBas Nieuwenhuizen }
7201331e630SBas Nieuwenhuizen
convert_tiling_flags_to_modifier(struct amdgpu_framebuffer * afb)72108d76915SBas Nieuwenhuizen static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
72208d76915SBas Nieuwenhuizen {
72308d76915SBas Nieuwenhuizen struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
72408d76915SBas Nieuwenhuizen uint64_t modifier = 0;
725543036a2SAurabindo Pillai int num_pipes = 0;
726543036a2SAurabindo Pillai int num_pkrs = 0;
727543036a2SAurabindo Pillai
728543036a2SAurabindo Pillai num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
729543036a2SAurabindo Pillai num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
73008d76915SBas Nieuwenhuizen
73108d76915SBas Nieuwenhuizen if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
73208d76915SBas Nieuwenhuizen modifier = DRM_FORMAT_MOD_LINEAR;
73308d76915SBas Nieuwenhuizen } else {
73408d76915SBas Nieuwenhuizen int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
73508d76915SBas Nieuwenhuizen bool has_xor = swizzle >= 16;
73608d76915SBas Nieuwenhuizen int block_size_bits;
73708d76915SBas Nieuwenhuizen int version;
73808d76915SBas Nieuwenhuizen int pipe_xor_bits = 0;
73908d76915SBas Nieuwenhuizen int bank_xor_bits = 0;
74008d76915SBas Nieuwenhuizen int packers = 0;
7411331e630SBas Nieuwenhuizen int rb = 0;
742543036a2SAurabindo Pillai int pipes = ilog2(num_pipes);
74308d76915SBas Nieuwenhuizen uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
74408d76915SBas Nieuwenhuizen
74508d76915SBas Nieuwenhuizen switch (swizzle >> 2) {
74608d76915SBas Nieuwenhuizen case 0: /* 256B */
74708d76915SBas Nieuwenhuizen block_size_bits = 8;
74808d76915SBas Nieuwenhuizen break;
74908d76915SBas Nieuwenhuizen case 1: /* 4KiB */
75008d76915SBas Nieuwenhuizen case 5: /* 4KiB _X */
75108d76915SBas Nieuwenhuizen block_size_bits = 12;
75208d76915SBas Nieuwenhuizen break;
75308d76915SBas Nieuwenhuizen case 2: /* 64KiB */
75408d76915SBas Nieuwenhuizen case 4: /* 64 KiB _T */
75508d76915SBas Nieuwenhuizen case 6: /* 64 KiB _X */
75608d76915SBas Nieuwenhuizen block_size_bits = 16;
75708d76915SBas Nieuwenhuizen break;
758543036a2SAurabindo Pillai case 7: /* 256 KiB */
759543036a2SAurabindo Pillai block_size_bits = 18;
760543036a2SAurabindo Pillai break;
76108d76915SBas Nieuwenhuizen default:
76208d76915SBas Nieuwenhuizen /* RESERVED or VAR */
76308d76915SBas Nieuwenhuizen return -EINVAL;
76408d76915SBas Nieuwenhuizen }
76508d76915SBas Nieuwenhuizen
766543036a2SAurabindo Pillai if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
767543036a2SAurabindo Pillai version = AMD_FMT_MOD_TILE_VER_GFX11;
768543036a2SAurabindo Pillai else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
76908d76915SBas Nieuwenhuizen version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
77045a3e06bSAlex Deucher else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
77108d76915SBas Nieuwenhuizen version = AMD_FMT_MOD_TILE_VER_GFX10;
77208d76915SBas Nieuwenhuizen else
77308d76915SBas Nieuwenhuizen version = AMD_FMT_MOD_TILE_VER_GFX9;
77408d76915SBas Nieuwenhuizen
77508d76915SBas Nieuwenhuizen switch (swizzle & 3) {
77608d76915SBas Nieuwenhuizen case 0: /* Z microtiling */
77708d76915SBas Nieuwenhuizen return -EINVAL;
77808d76915SBas Nieuwenhuizen case 1: /* S microtiling */
779543036a2SAurabindo Pillai if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
78008d76915SBas Nieuwenhuizen if (!has_xor)
78108d76915SBas Nieuwenhuizen version = AMD_FMT_MOD_TILE_VER_GFX9;
782543036a2SAurabindo Pillai }
78308d76915SBas Nieuwenhuizen break;
78408d76915SBas Nieuwenhuizen case 2:
785543036a2SAurabindo Pillai if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
78608d76915SBas Nieuwenhuizen if (!has_xor && afb->base.format->cpp[0] != 4)
78708d76915SBas Nieuwenhuizen version = AMD_FMT_MOD_TILE_VER_GFX9;
788543036a2SAurabindo Pillai }
78908d76915SBas Nieuwenhuizen break;
79008d76915SBas Nieuwenhuizen case 3:
79108d76915SBas Nieuwenhuizen break;
79208d76915SBas Nieuwenhuizen }
79308d76915SBas Nieuwenhuizen
79408d76915SBas Nieuwenhuizen if (has_xor) {
795543036a2SAurabindo Pillai if (num_pipes == num_pkrs && num_pkrs == 0) {
796543036a2SAurabindo Pillai DRM_ERROR("invalid number of pipes and packers\n");
797543036a2SAurabindo Pillai return -EINVAL;
798543036a2SAurabindo Pillai }
799543036a2SAurabindo Pillai
80008d76915SBas Nieuwenhuizen switch (version) {
801543036a2SAurabindo Pillai case AMD_FMT_MOD_TILE_VER_GFX11:
802543036a2SAurabindo Pillai pipe_xor_bits = min(block_size_bits - 8, pipes);
803ff15cea3SAurabindo Pillai packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
804543036a2SAurabindo Pillai break;
80508d76915SBas Nieuwenhuizen case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
8061331e630SBas Nieuwenhuizen pipe_xor_bits = min(block_size_bits - 8, pipes);
80708d76915SBas Nieuwenhuizen packers = min(block_size_bits - 8 - pipe_xor_bits,
80808d76915SBas Nieuwenhuizen ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
80908d76915SBas Nieuwenhuizen break;
81008d76915SBas Nieuwenhuizen case AMD_FMT_MOD_TILE_VER_GFX10:
8111331e630SBas Nieuwenhuizen pipe_xor_bits = min(block_size_bits - 8, pipes);
81208d76915SBas Nieuwenhuizen break;
81308d76915SBas Nieuwenhuizen case AMD_FMT_MOD_TILE_VER_GFX9:
8141331e630SBas Nieuwenhuizen rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
8151331e630SBas Nieuwenhuizen ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
8161331e630SBas Nieuwenhuizen pipe_xor_bits = min(block_size_bits - 8, pipes +
81708d76915SBas Nieuwenhuizen ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
81808d76915SBas Nieuwenhuizen bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
81908d76915SBas Nieuwenhuizen ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
82008d76915SBas Nieuwenhuizen break;
82108d76915SBas Nieuwenhuizen }
82208d76915SBas Nieuwenhuizen }
82308d76915SBas Nieuwenhuizen
82408d76915SBas Nieuwenhuizen modifier = AMD_FMT_MOD |
82508d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
82608d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(TILE_VERSION, version) |
82708d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
82808d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
82908d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(PACKERS, packers);
83008d76915SBas Nieuwenhuizen
83108d76915SBas Nieuwenhuizen if (dcc_offset != 0) {
83208d76915SBas Nieuwenhuizen bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
83308d76915SBas Nieuwenhuizen bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
834816853f9SBas Nieuwenhuizen const struct drm_format_info *format_info;
8351331e630SBas Nieuwenhuizen u64 render_dcc_offset;
83608d76915SBas Nieuwenhuizen
83708d76915SBas Nieuwenhuizen /* Enable constant encode on RAVEN2 and later. */
838543036a2SAurabindo Pillai bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
83908d76915SBas Nieuwenhuizen (adev->asic_type == CHIP_RAVEN &&
840543036a2SAurabindo Pillai adev->external_rev_id >= 0x81)) &&
841543036a2SAurabindo Pillai adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
84208d76915SBas Nieuwenhuizen
84308d76915SBas Nieuwenhuizen int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
84408d76915SBas Nieuwenhuizen dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
84508d76915SBas Nieuwenhuizen AMD_FMT_MOD_DCC_BLOCK_256B;
84608d76915SBas Nieuwenhuizen
84708d76915SBas Nieuwenhuizen modifier |= AMD_FMT_MOD_SET(DCC, 1) |
84808d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
84908d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
85008d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
85108d76915SBas Nieuwenhuizen AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
85208d76915SBas Nieuwenhuizen
85308d76915SBas Nieuwenhuizen afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
8541331e630SBas Nieuwenhuizen afb->base.pitches[1] =
8551331e630SBas Nieuwenhuizen AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
856816853f9SBas Nieuwenhuizen
8571331e630SBas Nieuwenhuizen /*
8581331e630SBas Nieuwenhuizen * If the userspace driver uses retiling the tiling flags do not contain
8591331e630SBas Nieuwenhuizen * info on the renderable DCC buffer. Luckily the opaque metadata contains
8601331e630SBas Nieuwenhuizen * the info so we can try to extract it. The kernel does not use this info
8611331e630SBas Nieuwenhuizen * but we should convert it to a modifier plane for getfb2, so the
8621331e630SBas Nieuwenhuizen * userspace driver that gets it doesn't have to juggle around another DCC
8631331e630SBas Nieuwenhuizen * plane internally.
8641331e630SBas Nieuwenhuizen */
8651331e630SBas Nieuwenhuizen if (extract_render_dcc_offset(adev, afb->base.obj[0],
8661331e630SBas Nieuwenhuizen &render_dcc_offset) == 0 &&
8671331e630SBas Nieuwenhuizen render_dcc_offset != 0 &&
8681331e630SBas Nieuwenhuizen render_dcc_offset != afb->base.offsets[1] &&
8691331e630SBas Nieuwenhuizen render_dcc_offset < UINT_MAX) {
8701331e630SBas Nieuwenhuizen uint32_t dcc_block_bits; /* of base surface data */
8711331e630SBas Nieuwenhuizen
8721331e630SBas Nieuwenhuizen modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
8731331e630SBas Nieuwenhuizen afb->base.offsets[2] = render_dcc_offset;
8741331e630SBas Nieuwenhuizen
8751331e630SBas Nieuwenhuizen if (adev->family >= AMDGPU_FAMILY_NV) {
8761331e630SBas Nieuwenhuizen int extra_pipe = 0;
8771331e630SBas Nieuwenhuizen
87845a3e06bSAlex Deucher if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
8791331e630SBas Nieuwenhuizen pipes == packers && pipes > 1)
8801331e630SBas Nieuwenhuizen extra_pipe = 1;
8811331e630SBas Nieuwenhuizen
8821331e630SBas Nieuwenhuizen dcc_block_bits = max(20, 16 + pipes + extra_pipe);
8831331e630SBas Nieuwenhuizen } else {
8841331e630SBas Nieuwenhuizen modifier |= AMD_FMT_MOD_SET(RB, rb) |
8851331e630SBas Nieuwenhuizen AMD_FMT_MOD_SET(PIPE, pipes);
8861331e630SBas Nieuwenhuizen dcc_block_bits = max(20, 18 + rb);
8871331e630SBas Nieuwenhuizen }
8881331e630SBas Nieuwenhuizen
8891331e630SBas Nieuwenhuizen dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
8901331e630SBas Nieuwenhuizen afb->base.pitches[2] = ALIGN(afb->base.width,
8911331e630SBas Nieuwenhuizen 1u << ((dcc_block_bits + 1) / 2));
8921331e630SBas Nieuwenhuizen }
893816853f9SBas Nieuwenhuizen format_info = amdgpu_lookup_format_info(afb->base.format->format,
894816853f9SBas Nieuwenhuizen modifier);
895816853f9SBas Nieuwenhuizen if (!format_info)
896816853f9SBas Nieuwenhuizen return -EINVAL;
897816853f9SBas Nieuwenhuizen
898816853f9SBas Nieuwenhuizen afb->base.format = format_info;
89908d76915SBas Nieuwenhuizen }
90008d76915SBas Nieuwenhuizen }
90108d76915SBas Nieuwenhuizen
90208d76915SBas Nieuwenhuizen afb->base.modifier = modifier;
90308d76915SBas Nieuwenhuizen afb->base.flags |= DRM_MODE_FB_MODIFIERS;
90408d76915SBas Nieuwenhuizen return 0;
90508d76915SBas Nieuwenhuizen }
90608d76915SBas Nieuwenhuizen
9072f350ddaSSimon Ser /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
check_tiling_flags_gfx6(struct amdgpu_framebuffer * afb)9082f350ddaSSimon Ser static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
9092f350ddaSSimon Ser {
9102f350ddaSSimon Ser u64 micro_tile_mode;
9112f350ddaSSimon Ser
9122f350ddaSSimon Ser /* Zero swizzle mode means linear */
9132f350ddaSSimon Ser if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
9142f350ddaSSimon Ser return 0;
9152f350ddaSSimon Ser
9162f350ddaSSimon Ser micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
9172f350ddaSSimon Ser switch (micro_tile_mode) {
9182f350ddaSSimon Ser case 0: /* DISPLAY */
9192f350ddaSSimon Ser case 3: /* RENDER */
9202f350ddaSSimon Ser return 0;
9212f350ddaSSimon Ser default:
9222f350ddaSSimon Ser drm_dbg_kms(afb->base.dev,
9232f350ddaSSimon Ser "Micro tile mode %llu not supported for scanout\n",
9242f350ddaSSimon Ser micro_tile_mode);
9252f350ddaSSimon Ser return -EINVAL;
9262f350ddaSSimon Ser }
9272f350ddaSSimon Ser }
9282f350ddaSSimon Ser
get_block_dimensions(unsigned int block_log2,unsigned int cpp,unsigned int * width,unsigned int * height)929234055fdSBas Nieuwenhuizen static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
930234055fdSBas Nieuwenhuizen unsigned int *width, unsigned int *height)
931234055fdSBas Nieuwenhuizen {
932234055fdSBas Nieuwenhuizen unsigned int cpp_log2 = ilog2(cpp);
933234055fdSBas Nieuwenhuizen unsigned int pixel_log2 = block_log2 - cpp_log2;
934234055fdSBas Nieuwenhuizen unsigned int width_log2 = (pixel_log2 + 1) / 2;
935234055fdSBas Nieuwenhuizen unsigned int height_log2 = pixel_log2 - width_log2;
936234055fdSBas Nieuwenhuizen
937234055fdSBas Nieuwenhuizen *width = 1 << width_log2;
938234055fdSBas Nieuwenhuizen *height = 1 << height_log2;
939234055fdSBas Nieuwenhuizen }
940234055fdSBas Nieuwenhuizen
get_dcc_block_size(uint64_t modifier,bool rb_aligned,bool pipe_aligned)941234055fdSBas Nieuwenhuizen static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
942234055fdSBas Nieuwenhuizen bool pipe_aligned)
943234055fdSBas Nieuwenhuizen {
944234055fdSBas Nieuwenhuizen unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
945234055fdSBas Nieuwenhuizen
946234055fdSBas Nieuwenhuizen switch (ver) {
947234055fdSBas Nieuwenhuizen case AMD_FMT_MOD_TILE_VER_GFX9: {
948234055fdSBas Nieuwenhuizen /*
949234055fdSBas Nieuwenhuizen * TODO: for pipe aligned we may need to check the alignment of the
950234055fdSBas Nieuwenhuizen * total size of the surface, which may need to be bigger than the
951234055fdSBas Nieuwenhuizen * natural alignment due to some HW workarounds
952234055fdSBas Nieuwenhuizen */
953234055fdSBas Nieuwenhuizen return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
954234055fdSBas Nieuwenhuizen }
955234055fdSBas Nieuwenhuizen case AMD_FMT_MOD_TILE_VER_GFX10:
956543036a2SAurabindo Pillai case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
957543036a2SAurabindo Pillai case AMD_FMT_MOD_TILE_VER_GFX11: {
958234055fdSBas Nieuwenhuizen int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
959234055fdSBas Nieuwenhuizen
960543036a2SAurabindo Pillai if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
961234055fdSBas Nieuwenhuizen AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
962234055fdSBas Nieuwenhuizen ++pipes_log2;
963234055fdSBas Nieuwenhuizen
964234055fdSBas Nieuwenhuizen return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
965234055fdSBas Nieuwenhuizen }
966234055fdSBas Nieuwenhuizen default:
967234055fdSBas Nieuwenhuizen return 0;
968234055fdSBas Nieuwenhuizen }
969234055fdSBas Nieuwenhuizen }
970234055fdSBas Nieuwenhuizen
amdgpu_display_verify_plane(struct amdgpu_framebuffer * rfb,int plane,const struct drm_format_info * format,unsigned int block_width,unsigned int block_height,unsigned int block_size_log2)971234055fdSBas Nieuwenhuizen static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
972234055fdSBas Nieuwenhuizen const struct drm_format_info *format,
973234055fdSBas Nieuwenhuizen unsigned int block_width, unsigned int block_height,
974234055fdSBas Nieuwenhuizen unsigned int block_size_log2)
975234055fdSBas Nieuwenhuizen {
976234055fdSBas Nieuwenhuizen unsigned int width = rfb->base.width /
977234055fdSBas Nieuwenhuizen ((plane && plane < format->num_planes) ? format->hsub : 1);
978234055fdSBas Nieuwenhuizen unsigned int height = rfb->base.height /
979234055fdSBas Nieuwenhuizen ((plane && plane < format->num_planes) ? format->vsub : 1);
980234055fdSBas Nieuwenhuizen unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
981234055fdSBas Nieuwenhuizen unsigned int block_pitch = block_width * cpp;
982234055fdSBas Nieuwenhuizen unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
983234055fdSBas Nieuwenhuizen unsigned int block_size = 1 << block_size_log2;
984234055fdSBas Nieuwenhuizen uint64_t size;
985234055fdSBas Nieuwenhuizen
986234055fdSBas Nieuwenhuizen if (rfb->base.pitches[plane] % block_pitch) {
987234055fdSBas Nieuwenhuizen drm_dbg_kms(rfb->base.dev,
988234055fdSBas Nieuwenhuizen "pitch %d for plane %d is not a multiple of block pitch %d\n",
989234055fdSBas Nieuwenhuizen rfb->base.pitches[plane], plane, block_pitch);
990234055fdSBas Nieuwenhuizen return -EINVAL;
991234055fdSBas Nieuwenhuizen }
992234055fdSBas Nieuwenhuizen if (rfb->base.pitches[plane] < min_pitch) {
993234055fdSBas Nieuwenhuizen drm_dbg_kms(rfb->base.dev,
994234055fdSBas Nieuwenhuizen "pitch %d for plane %d is less than minimum pitch %d\n",
995234055fdSBas Nieuwenhuizen rfb->base.pitches[plane], plane, min_pitch);
996234055fdSBas Nieuwenhuizen return -EINVAL;
997234055fdSBas Nieuwenhuizen }
998234055fdSBas Nieuwenhuizen
999234055fdSBas Nieuwenhuizen /* Force at least natural alignment. */
1000234055fdSBas Nieuwenhuizen if (rfb->base.offsets[plane] % block_size) {
1001234055fdSBas Nieuwenhuizen drm_dbg_kms(rfb->base.dev,
1002234055fdSBas Nieuwenhuizen "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
1003234055fdSBas Nieuwenhuizen rfb->base.offsets[plane], plane, block_size);
1004234055fdSBas Nieuwenhuizen return -EINVAL;
1005234055fdSBas Nieuwenhuizen }
1006234055fdSBas Nieuwenhuizen
1007234055fdSBas Nieuwenhuizen size = rfb->base.offsets[plane] +
1008234055fdSBas Nieuwenhuizen (uint64_t)rfb->base.pitches[plane] / block_pitch *
1009234055fdSBas Nieuwenhuizen block_size * DIV_ROUND_UP(height, block_height);
1010234055fdSBas Nieuwenhuizen
1011234055fdSBas Nieuwenhuizen if (rfb->base.obj[0]->size < size) {
1012234055fdSBas Nieuwenhuizen drm_dbg_kms(rfb->base.dev,
1013234055fdSBas Nieuwenhuizen "BO size 0x%zx is less than 0x%llx required for plane %d\n",
1014234055fdSBas Nieuwenhuizen rfb->base.obj[0]->size, size, plane);
1015234055fdSBas Nieuwenhuizen return -EINVAL;
1016234055fdSBas Nieuwenhuizen }
1017234055fdSBas Nieuwenhuizen
1018234055fdSBas Nieuwenhuizen return 0;
1019234055fdSBas Nieuwenhuizen }
1020234055fdSBas Nieuwenhuizen
1021234055fdSBas Nieuwenhuizen
amdgpu_display_verify_sizes(struct amdgpu_framebuffer * rfb)1022234055fdSBas Nieuwenhuizen static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
1023234055fdSBas Nieuwenhuizen {
1024234055fdSBas Nieuwenhuizen const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
1025234055fdSBas Nieuwenhuizen uint64_t modifier = rfb->base.modifier;
1026234055fdSBas Nieuwenhuizen int ret;
1027234055fdSBas Nieuwenhuizen unsigned int i, block_width, block_height, block_size_log2;
1028234055fdSBas Nieuwenhuizen
10292af10429STomohito Esaki if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
1030234055fdSBas Nieuwenhuizen return 0;
1031234055fdSBas Nieuwenhuizen
1032234055fdSBas Nieuwenhuizen for (i = 0; i < format_info->num_planes; ++i) {
1033234055fdSBas Nieuwenhuizen if (modifier == DRM_FORMAT_MOD_LINEAR) {
1034234055fdSBas Nieuwenhuizen block_width = 256 / format_info->cpp[i];
1035234055fdSBas Nieuwenhuizen block_height = 1;
1036234055fdSBas Nieuwenhuizen block_size_log2 = 8;
1037234055fdSBas Nieuwenhuizen } else {
1038234055fdSBas Nieuwenhuizen int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1039234055fdSBas Nieuwenhuizen
1040234055fdSBas Nieuwenhuizen switch ((swizzle & ~3) + 1) {
1041234055fdSBas Nieuwenhuizen case DC_SW_256B_S:
1042234055fdSBas Nieuwenhuizen block_size_log2 = 8;
1043234055fdSBas Nieuwenhuizen break;
1044234055fdSBas Nieuwenhuizen case DC_SW_4KB_S:
1045234055fdSBas Nieuwenhuizen case DC_SW_4KB_S_X:
1046234055fdSBas Nieuwenhuizen block_size_log2 = 12;
1047234055fdSBas Nieuwenhuizen break;
1048234055fdSBas Nieuwenhuizen case DC_SW_64KB_S:
1049234055fdSBas Nieuwenhuizen case DC_SW_64KB_S_T:
1050234055fdSBas Nieuwenhuizen case DC_SW_64KB_S_X:
1051234055fdSBas Nieuwenhuizen block_size_log2 = 16;
1052234055fdSBas Nieuwenhuizen break;
1053543036a2SAurabindo Pillai case DC_SW_VAR_S_X:
1054543036a2SAurabindo Pillai block_size_log2 = 18;
1055543036a2SAurabindo Pillai break;
1056234055fdSBas Nieuwenhuizen default:
1057234055fdSBas Nieuwenhuizen drm_dbg_kms(rfb->base.dev,
1058234055fdSBas Nieuwenhuizen "Swizzle mode with unknown block size: %d\n", swizzle);
1059234055fdSBas Nieuwenhuizen return -EINVAL;
1060234055fdSBas Nieuwenhuizen }
1061234055fdSBas Nieuwenhuizen
1062234055fdSBas Nieuwenhuizen get_block_dimensions(block_size_log2, format_info->cpp[i],
1063234055fdSBas Nieuwenhuizen &block_width, &block_height);
1064234055fdSBas Nieuwenhuizen }
1065234055fdSBas Nieuwenhuizen
1066234055fdSBas Nieuwenhuizen ret = amdgpu_display_verify_plane(rfb, i, format_info,
1067234055fdSBas Nieuwenhuizen block_width, block_height, block_size_log2);
1068234055fdSBas Nieuwenhuizen if (ret)
1069234055fdSBas Nieuwenhuizen return ret;
1070234055fdSBas Nieuwenhuizen }
1071234055fdSBas Nieuwenhuizen
1072234055fdSBas Nieuwenhuizen if (AMD_FMT_MOD_GET(DCC, modifier)) {
1073234055fdSBas Nieuwenhuizen if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1074234055fdSBas Nieuwenhuizen block_size_log2 = get_dcc_block_size(modifier, false, false);
1075234055fdSBas Nieuwenhuizen get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1076234055fdSBas Nieuwenhuizen &block_width, &block_height);
1077234055fdSBas Nieuwenhuizen ret = amdgpu_display_verify_plane(rfb, i, format_info,
1078234055fdSBas Nieuwenhuizen block_width, block_height,
1079234055fdSBas Nieuwenhuizen block_size_log2);
1080234055fdSBas Nieuwenhuizen if (ret)
1081234055fdSBas Nieuwenhuizen return ret;
1082234055fdSBas Nieuwenhuizen
1083234055fdSBas Nieuwenhuizen ++i;
1084234055fdSBas Nieuwenhuizen block_size_log2 = get_dcc_block_size(modifier, true, true);
1085234055fdSBas Nieuwenhuizen } else {
1086234055fdSBas Nieuwenhuizen bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1087234055fdSBas Nieuwenhuizen
1088234055fdSBas Nieuwenhuizen block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1089234055fdSBas Nieuwenhuizen }
1090234055fdSBas Nieuwenhuizen get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1091234055fdSBas Nieuwenhuizen &block_width, &block_height);
1092234055fdSBas Nieuwenhuizen ret = amdgpu_display_verify_plane(rfb, i, format_info,
1093234055fdSBas Nieuwenhuizen block_width, block_height, block_size_log2);
1094234055fdSBas Nieuwenhuizen if (ret)
1095234055fdSBas Nieuwenhuizen return ret;
1096234055fdSBas Nieuwenhuizen }
1097234055fdSBas Nieuwenhuizen
1098234055fdSBas Nieuwenhuizen return 0;
1099234055fdSBas Nieuwenhuizen }
1100234055fdSBas Nieuwenhuizen
amdgpu_display_get_fb_info(const struct amdgpu_framebuffer * amdgpu_fb,uint64_t * tiling_flags,bool * tmz_surface)11016eed95b0SBas Nieuwenhuizen static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
11026eed95b0SBas Nieuwenhuizen uint64_t *tiling_flags, bool *tmz_surface)
11036eed95b0SBas Nieuwenhuizen {
11046eed95b0SBas Nieuwenhuizen struct amdgpu_bo *rbo;
11056eed95b0SBas Nieuwenhuizen int r;
11066eed95b0SBas Nieuwenhuizen
11076eed95b0SBas Nieuwenhuizen if (!amdgpu_fb) {
11086eed95b0SBas Nieuwenhuizen *tiling_flags = 0;
11096eed95b0SBas Nieuwenhuizen *tmz_surface = false;
11106eed95b0SBas Nieuwenhuizen return 0;
11116eed95b0SBas Nieuwenhuizen }
11126eed95b0SBas Nieuwenhuizen
11136eed95b0SBas Nieuwenhuizen rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
11146eed95b0SBas Nieuwenhuizen r = amdgpu_bo_reserve(rbo, false);
11156eed95b0SBas Nieuwenhuizen
11166eed95b0SBas Nieuwenhuizen if (unlikely(r)) {
11176eed95b0SBas Nieuwenhuizen /* Don't show error message when returning -ERESTARTSYS */
11186eed95b0SBas Nieuwenhuizen if (r != -ERESTARTSYS)
11196eed95b0SBas Nieuwenhuizen DRM_ERROR("Unable to reserve buffer: %d\n", r);
11206eed95b0SBas Nieuwenhuizen return r;
11216eed95b0SBas Nieuwenhuizen }
11226eed95b0SBas Nieuwenhuizen
11236eed95b0SBas Nieuwenhuizen if (tiling_flags)
11246eed95b0SBas Nieuwenhuizen amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
11256eed95b0SBas Nieuwenhuizen
11266eed95b0SBas Nieuwenhuizen if (tmz_surface)
11276eed95b0SBas Nieuwenhuizen *tmz_surface = amdgpu_bo_encrypted(rbo);
11286eed95b0SBas Nieuwenhuizen
11296eed95b0SBas Nieuwenhuizen amdgpu_bo_unreserve(rbo);
11306eed95b0SBas Nieuwenhuizen
11316eed95b0SBas Nieuwenhuizen return r;
11326eed95b0SBas Nieuwenhuizen }
11336eed95b0SBas Nieuwenhuizen
amdgpu_display_gem_fb_verify_and_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1134c5b26681SAlex Deucher static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1135f258907fSMark Yacoub struct amdgpu_framebuffer *rfb,
1136c5b26681SAlex Deucher struct drm_file *file_priv,
1137f258907fSMark Yacoub const struct drm_mode_fb_cmd2 *mode_cmd,
1138f258907fSMark Yacoub struct drm_gem_object *obj)
1139f258907fSMark Yacoub {
1140f258907fSMark Yacoub int ret;
1141f258907fSMark Yacoub
1142f258907fSMark Yacoub rfb->base.obj[0] = obj;
1143f258907fSMark Yacoub drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1144fe180178SQingqing Zhuo /* Verify that the modifier is supported. */
1145fe180178SQingqing Zhuo if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1146fe180178SQingqing Zhuo mode_cmd->modifier[0])) {
1147fe180178SQingqing Zhuo drm_dbg_kms(dev,
11485a6af54dSThomas Zimmermann "unsupported pixel format %p4cc / modifier 0x%llx\n",
11495a6af54dSThomas Zimmermann &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1150fe180178SQingqing Zhuo
1151fe180178SQingqing Zhuo ret = -EINVAL;
1152fe180178SQingqing Zhuo goto err;
1153fe180178SQingqing Zhuo }
1154f258907fSMark Yacoub
1155f258907fSMark Yacoub ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1156f258907fSMark Yacoub if (ret)
1157f258907fSMark Yacoub goto err;
1158f258907fSMark Yacoub
11590a611560SHamza Mahfooz if (drm_drv_uses_atomic_modeset(dev))
11600a611560SHamza Mahfooz ret = drm_framebuffer_init(dev, &rfb->base,
11610a611560SHamza Mahfooz &amdgpu_fb_funcs_atomic);
11620a611560SHamza Mahfooz else
116324981fa3SMichel Dänzer ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
116417d819e2SHamza Mahfooz
116524981fa3SMichel Dänzer if (ret)
116624981fa3SMichel Dänzer goto err;
116724981fa3SMichel Dänzer
1168f258907fSMark Yacoub return 0;
1169f258907fSMark Yacoub err:
117032d6378cSMichel Dänzer drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1171f258907fSMark Yacoub rfb->base.obj[0] = NULL;
1172f258907fSMark Yacoub return ret;
1173f258907fSMark Yacoub }
1174f258907fSMark Yacoub
amdgpu_display_framebuffer_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)117531d5c523SAlex Deucher static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1176d38ceaf9SAlex Deucher struct amdgpu_framebuffer *rfb,
11771eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd,
1178d38ceaf9SAlex Deucher struct drm_gem_object *obj)
1179d38ceaf9SAlex Deucher {
11802f350ddaSSimon Ser struct amdgpu_device *adev = drm_to_adev(dev);
11813505b2ffSBas Nieuwenhuizen int ret, i;
11826eed95b0SBas Nieuwenhuizen
11833505b2ffSBas Nieuwenhuizen /*
11843505b2ffSBas Nieuwenhuizen * This needs to happen before modifier conversion as that might change
11853505b2ffSBas Nieuwenhuizen * the number of planes.
11863505b2ffSBas Nieuwenhuizen */
11873505b2ffSBas Nieuwenhuizen for (i = 1; i < rfb->base.format->num_planes; ++i) {
11883505b2ffSBas Nieuwenhuizen if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1189ccac8babSSimon Ser drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
11903505b2ffSBas Nieuwenhuizen i, mode_cmd->handles[0], mode_cmd->handles[i]);
11913505b2ffSBas Nieuwenhuizen ret = -EINVAL;
1192f258907fSMark Yacoub return ret;
11933505b2ffSBas Nieuwenhuizen }
11943505b2ffSBas Nieuwenhuizen }
11953505b2ffSBas Nieuwenhuizen
11966eed95b0SBas Nieuwenhuizen ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
11976eed95b0SBas Nieuwenhuizen if (ret)
1198f258907fSMark Yacoub return ret;
11996eed95b0SBas Nieuwenhuizen
12006c64ae22SDave Airlie if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
12012f350ddaSSimon Ser drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
12022f350ddaSSimon Ser "GFX9+ requires FB check based on format modifier\n");
12032f350ddaSSimon Ser ret = check_tiling_flags_gfx6(rfb);
12042f350ddaSSimon Ser if (ret)
12052f350ddaSSimon Ser return ret;
12062f350ddaSSimon Ser }
12072f350ddaSSimon Ser
12082af10429STomohito Esaki if (!dev->mode_config.fb_modifiers_not_supported &&
120908d76915SBas Nieuwenhuizen !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
121008d76915SBas Nieuwenhuizen ret = convert_tiling_flags_to_modifier(rfb);
1211048faf27SSimon Ser if (ret) {
1212048faf27SSimon Ser drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1213048faf27SSimon Ser rfb->tiling_flags);
1214f258907fSMark Yacoub return ret;
121508d76915SBas Nieuwenhuizen }
1216048faf27SSimon Ser }
121708d76915SBas Nieuwenhuizen
1218234055fdSBas Nieuwenhuizen ret = amdgpu_display_verify_sizes(rfb);
1219234055fdSBas Nieuwenhuizen if (ret)
1220234055fdSBas Nieuwenhuizen return ret;
1221234055fdSBas Nieuwenhuizen
1222234055fdSBas Nieuwenhuizen for (i = 0; i < rfb->base.format->num_planes; ++i) {
122379fcd446Sxinhui pan drm_gem_object_get(rfb->base.obj[0]);
12243505b2ffSBas Nieuwenhuizen rfb->base.obj[i] = rfb->base.obj[0];
12253505b2ffSBas Nieuwenhuizen }
12263505b2ffSBas Nieuwenhuizen
12276eed95b0SBas Nieuwenhuizen return 0;
1228d38ceaf9SAlex Deucher }
1229d38ceaf9SAlex Deucher
1230b0fb632fSHarry Wentland struct drm_framebuffer *
amdgpu_display_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)12314d4772f6SSamuel Li amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1232d38ceaf9SAlex Deucher struct drm_file *file_priv,
12331eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd)
1234d38ceaf9SAlex Deucher {
1235d38ceaf9SAlex Deucher struct amdgpu_framebuffer *amdgpu_fb;
1236dd017d01SChristian König struct drm_gem_object *obj;
1237dd017d01SChristian König struct amdgpu_bo *bo;
1238dd017d01SChristian König uint32_t domains;
1239d38ceaf9SAlex Deucher int ret;
1240d38ceaf9SAlex Deucher
1241a8ad0bd8SChris Wilson obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1242d38ceaf9SAlex Deucher if (obj == NULL) {
124393125cb7SSrinivasan Shanmugam drm_dbg_kms(dev,
124493125cb7SSrinivasan Shanmugam "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
124593125cb7SSrinivasan Shanmugam mode_cmd->handles[0]);
124693125cb7SSrinivasan Shanmugam
1247d38ceaf9SAlex Deucher return ERR_PTR(-ENOENT);
1248d38ceaf9SAlex Deucher }
1249d38ceaf9SAlex Deucher
12501769152aSChristopher James Halse Rogers /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1251dd017d01SChristian König bo = gem_to_amdgpu_bo(obj);
1252dd017d01SChristian König domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1253dd017d01SChristian König if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1254ccac8babSSimon Ser drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1255e0c16eb4SSimon Ser drm_gem_object_put(obj);
12561769152aSChristopher James Halse Rogers return ERR_PTR(-EINVAL);
12571769152aSChristopher James Halse Rogers }
12581769152aSChristopher James Halse Rogers
1259d38ceaf9SAlex Deucher amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1260d38ceaf9SAlex Deucher if (amdgpu_fb == NULL) {
1261e07ddb0cSEmil Velikov drm_gem_object_put(obj);
1262d38ceaf9SAlex Deucher return ERR_PTR(-ENOMEM);
1263d38ceaf9SAlex Deucher }
1264d38ceaf9SAlex Deucher
1265f258907fSMark Yacoub ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1266f258907fSMark Yacoub mode_cmd, obj);
1267d38ceaf9SAlex Deucher if (ret) {
1268d38ceaf9SAlex Deucher kfree(amdgpu_fb);
1269e07ddb0cSEmil Velikov drm_gem_object_put(obj);
1270d38ceaf9SAlex Deucher return ERR_PTR(ret);
1271d38ceaf9SAlex Deucher }
1272d38ceaf9SAlex Deucher
127379fcd446Sxinhui pan drm_gem_object_put(obj);
1274d38ceaf9SAlex Deucher return &amdgpu_fb->base;
1275d38ceaf9SAlex Deucher }
1276d38ceaf9SAlex Deucher
1277d38ceaf9SAlex Deucher const struct drm_mode_config_funcs amdgpu_mode_funcs = {
12784d4772f6SSamuel Li .fb_create = amdgpu_display_user_framebuffer_create,
1279d38ceaf9SAlex Deucher };
1280d38ceaf9SAlex Deucher
1281b2edaac4SSrinivasan Shanmugam static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = {
1282b2edaac4SSrinivasan Shanmugam { UNDERSCAN_OFF, "off" },
1283d38ceaf9SAlex Deucher { UNDERSCAN_ON, "on" },
1284d38ceaf9SAlex Deucher { UNDERSCAN_AUTO, "auto" },
1285d38ceaf9SAlex Deucher };
1286d38ceaf9SAlex Deucher
1287b2edaac4SSrinivasan Shanmugam static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = {
1288b2edaac4SSrinivasan Shanmugam { AMDGPU_AUDIO_DISABLE, "off" },
1289d38ceaf9SAlex Deucher { AMDGPU_AUDIO_ENABLE, "on" },
1290d38ceaf9SAlex Deucher { AMDGPU_AUDIO_AUTO, "auto" },
1291d38ceaf9SAlex Deucher };
1292d38ceaf9SAlex Deucher
1293d38ceaf9SAlex Deucher /* XXX support different dither options? spatial, temporal, both, etc. */
1294b2edaac4SSrinivasan Shanmugam static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = {
1295b2edaac4SSrinivasan Shanmugam { AMDGPU_FMT_DITHER_DISABLE, "off" },
1296d38ceaf9SAlex Deucher { AMDGPU_FMT_DITHER_ENABLE, "on" },
1297d38ceaf9SAlex Deucher };
1298d38ceaf9SAlex Deucher
amdgpu_display_modeset_create_props(struct amdgpu_device * adev)12993dc9b1ceSSamuel Li int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1300d38ceaf9SAlex Deucher {
1301d38ceaf9SAlex Deucher int sz;
1302d38ceaf9SAlex Deucher
1303d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property =
13044a580877SLuben Tuikov drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1305d38ceaf9SAlex Deucher if (!adev->mode_info.coherent_mode_property)
1306d38ceaf9SAlex Deucher return -ENOMEM;
1307d38ceaf9SAlex Deucher
1308d38ceaf9SAlex Deucher adev->mode_info.load_detect_property =
13094a580877SLuben Tuikov drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1310d38ceaf9SAlex Deucher if (!adev->mode_info.load_detect_property)
1311d38ceaf9SAlex Deucher return -ENOMEM;
1312d38ceaf9SAlex Deucher
13134a580877SLuben Tuikov drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1314d38ceaf9SAlex Deucher
1315d38ceaf9SAlex Deucher sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1316d38ceaf9SAlex Deucher adev->mode_info.underscan_property =
13174a580877SLuben Tuikov drm_property_create_enum(adev_to_drm(adev), 0,
1318d38ceaf9SAlex Deucher "underscan",
1319d38ceaf9SAlex Deucher amdgpu_underscan_enum_list, sz);
1320d38ceaf9SAlex Deucher
1321d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property =
13224a580877SLuben Tuikov drm_property_create_range(adev_to_drm(adev), 0,
1323d38ceaf9SAlex Deucher "underscan hborder", 0, 128);
1324d38ceaf9SAlex Deucher if (!adev->mode_info.underscan_hborder_property)
1325d38ceaf9SAlex Deucher return -ENOMEM;
1326d38ceaf9SAlex Deucher
1327d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property =
13284a580877SLuben Tuikov drm_property_create_range(adev_to_drm(adev), 0,
1329d38ceaf9SAlex Deucher "underscan vborder", 0, 128);
1330d38ceaf9SAlex Deucher if (!adev->mode_info.underscan_vborder_property)
1331d38ceaf9SAlex Deucher return -ENOMEM;
1332d38ceaf9SAlex Deucher
1333d38ceaf9SAlex Deucher sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1334d38ceaf9SAlex Deucher adev->mode_info.audio_property =
13354a580877SLuben Tuikov drm_property_create_enum(adev_to_drm(adev), 0,
1336d38ceaf9SAlex Deucher "audio",
1337d38ceaf9SAlex Deucher amdgpu_audio_enum_list, sz);
1338d38ceaf9SAlex Deucher
1339d38ceaf9SAlex Deucher sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1340d38ceaf9SAlex Deucher adev->mode_info.dither_property =
13414a580877SLuben Tuikov drm_property_create_enum(adev_to_drm(adev), 0,
1342d38ceaf9SAlex Deucher "dither",
1343d38ceaf9SAlex Deucher amdgpu_dither_enum_list, sz);
1344d38ceaf9SAlex Deucher
1345d09ef243SAlex Deucher if (adev->dc_enabled) {
1346c1ee92f9SDavid Francis adev->mode_info.abm_level_property =
13474a580877SLuben Tuikov drm_property_create_range(adev_to_drm(adev), 0,
1348c1ee92f9SDavid Francis "abm level", 0, 4);
1349c1ee92f9SDavid Francis if (!adev->mode_info.abm_level_property)
1350c1ee92f9SDavid Francis return -ENOMEM;
1351e2306cc6SNicholas Kazlauskas }
1352e2306cc6SNicholas Kazlauskas
1353d38ceaf9SAlex Deucher return 0;
1354d38ceaf9SAlex Deucher }
1355d38ceaf9SAlex Deucher
amdgpu_display_update_priority(struct amdgpu_device * adev)1356166140fbSSamuel Li void amdgpu_display_update_priority(struct amdgpu_device *adev)
1357d38ceaf9SAlex Deucher {
1358d38ceaf9SAlex Deucher /* adjustment options for the display watermarks */
1359d38ceaf9SAlex Deucher if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1360d38ceaf9SAlex Deucher adev->mode_info.disp_priority = 0;
1361d38ceaf9SAlex Deucher else
1362d38ceaf9SAlex Deucher adev->mode_info.disp_priority = amdgpu_disp_priority;
1363d38ceaf9SAlex Deucher
1364d38ceaf9SAlex Deucher }
1365d38ceaf9SAlex Deucher
amdgpu_display_is_hdtv_mode(const struct drm_display_mode * mode)13663a05dc00SSamuel Li static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1367d38ceaf9SAlex Deucher {
1368d38ceaf9SAlex Deucher /* try and guess if this is a tv or a monitor */
1369d38ceaf9SAlex Deucher if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1370d38ceaf9SAlex Deucher (mode->vdisplay == 576) || /* 576p */
1371d38ceaf9SAlex Deucher (mode->vdisplay == 720) || /* 720p */
1372d38ceaf9SAlex Deucher (mode->vdisplay == 1080)) /* 1080p */
1373d38ceaf9SAlex Deucher return true;
1374d38ceaf9SAlex Deucher else
1375d38ceaf9SAlex Deucher return false;
1376d38ceaf9SAlex Deucher }
1377d38ceaf9SAlex Deucher
amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)13780c16443aSSamuel Li bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1379d38ceaf9SAlex Deucher const struct drm_display_mode *mode,
1380d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode)
1381d38ceaf9SAlex Deucher {
1382d38ceaf9SAlex Deucher struct drm_device *dev = crtc->dev;
1383d38ceaf9SAlex Deucher struct drm_encoder *encoder;
1384d38ceaf9SAlex Deucher struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1385d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
1386d38ceaf9SAlex Deucher struct drm_connector *connector;
1387d38ceaf9SAlex Deucher u32 src_v = 1, dst_v = 1;
1388d38ceaf9SAlex Deucher u32 src_h = 1, dst_h = 1;
1389d38ceaf9SAlex Deucher
1390d38ceaf9SAlex Deucher amdgpu_crtc->h_border = 0;
1391d38ceaf9SAlex Deucher amdgpu_crtc->v_border = 0;
1392d38ceaf9SAlex Deucher
1393d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1394d38ceaf9SAlex Deucher if (encoder->crtc != crtc)
1395d38ceaf9SAlex Deucher continue;
1396d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
1397d38ceaf9SAlex Deucher connector = amdgpu_get_connector_for_encoder(encoder);
1398d38ceaf9SAlex Deucher
1399d38ceaf9SAlex Deucher /* set scaling */
1400d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF)
1401d38ceaf9SAlex Deucher amdgpu_crtc->rmx_type = RMX_OFF;
1402d38ceaf9SAlex Deucher else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1403d38ceaf9SAlex Deucher mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1404d38ceaf9SAlex Deucher amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1405d38ceaf9SAlex Deucher else
1406d38ceaf9SAlex Deucher amdgpu_crtc->rmx_type = RMX_OFF;
1407d38ceaf9SAlex Deucher /* copy native mode */
1408d38ceaf9SAlex Deucher memcpy(&amdgpu_crtc->native_mode,
1409d38ceaf9SAlex Deucher &amdgpu_encoder->native_mode,
1410d38ceaf9SAlex Deucher sizeof(struct drm_display_mode));
1411d38ceaf9SAlex Deucher src_v = crtc->mode.vdisplay;
1412d38ceaf9SAlex Deucher dst_v = amdgpu_crtc->native_mode.vdisplay;
1413d38ceaf9SAlex Deucher src_h = crtc->mode.hdisplay;
1414d38ceaf9SAlex Deucher dst_h = amdgpu_crtc->native_mode.hdisplay;
1415d38ceaf9SAlex Deucher
1416d38ceaf9SAlex Deucher /* fix up for overscan on hdmi */
1417d38ceaf9SAlex Deucher if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1418d38ceaf9SAlex Deucher ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1419d38ceaf9SAlex Deucher ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
14203c021931SClaudio Suarez connector->display_info.is_hdmi &&
14213a05dc00SSamuel Li amdgpu_display_is_hdtv_mode(mode)))) {
1422d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != 0)
1423d38ceaf9SAlex Deucher amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1424d38ceaf9SAlex Deucher else
1425d38ceaf9SAlex Deucher amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1426d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != 0)
1427d38ceaf9SAlex Deucher amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1428d38ceaf9SAlex Deucher else
1429d38ceaf9SAlex Deucher amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1430d38ceaf9SAlex Deucher amdgpu_crtc->rmx_type = RMX_FULL;
1431d38ceaf9SAlex Deucher src_v = crtc->mode.vdisplay;
1432d38ceaf9SAlex Deucher dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1433d38ceaf9SAlex Deucher src_h = crtc->mode.hdisplay;
1434d38ceaf9SAlex Deucher dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1435d38ceaf9SAlex Deucher }
1436d38ceaf9SAlex Deucher }
1437d38ceaf9SAlex Deucher if (amdgpu_crtc->rmx_type != RMX_OFF) {
1438d38ceaf9SAlex Deucher fixed20_12 a, b;
143993125cb7SSrinivasan Shanmugam
1440d38ceaf9SAlex Deucher a.full = dfixed_const(src_v);
1441d38ceaf9SAlex Deucher b.full = dfixed_const(dst_v);
1442d38ceaf9SAlex Deucher amdgpu_crtc->vsc.full = dfixed_div(a, b);
1443d38ceaf9SAlex Deucher a.full = dfixed_const(src_h);
1444d38ceaf9SAlex Deucher b.full = dfixed_const(dst_h);
1445d38ceaf9SAlex Deucher amdgpu_crtc->hsc.full = dfixed_div(a, b);
1446d38ceaf9SAlex Deucher } else {
1447d38ceaf9SAlex Deucher amdgpu_crtc->vsc.full = dfixed_const(1);
1448d38ceaf9SAlex Deucher amdgpu_crtc->hsc.full = dfixed_const(1);
1449d38ceaf9SAlex Deucher }
1450d38ceaf9SAlex Deucher return true;
1451d38ceaf9SAlex Deucher }
1452d38ceaf9SAlex Deucher
1453d38ceaf9SAlex Deucher /*
1454d38ceaf9SAlex Deucher * Retrieve current video scanout position of crtc on a given gpu, and
1455d38ceaf9SAlex Deucher * an optional accurate timestamp of when query happened.
1456d38ceaf9SAlex Deucher *
1457d38ceaf9SAlex Deucher * \param dev Device to query.
145888e72717SThierry Reding * \param pipe Crtc to query.
145993125cb7SSrinivasan Shanmugam * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
14608e36f9d3SAlex Deucher * For driver internal use only also supports these flags:
14618e36f9d3SAlex Deucher *
14628e36f9d3SAlex Deucher * USE_REAL_VBLANKSTART to use the real start of vblank instead
14638e36f9d3SAlex Deucher * of a fudged earlier start of vblank.
14648e36f9d3SAlex Deucher *
14658e36f9d3SAlex Deucher * GET_DISTANCE_TO_VBLANKSTART to return distance to the
14668e36f9d3SAlex Deucher * fudged earlier start of vblank in *vpos and the distance
14678e36f9d3SAlex Deucher * to true start of vblank in *hpos.
14688e36f9d3SAlex Deucher *
1469d38ceaf9SAlex Deucher * \param *vpos Location where vertical scanout position should be stored.
1470d38ceaf9SAlex Deucher * \param *hpos Location where horizontal scanout position should go.
1471d38ceaf9SAlex Deucher * \param *stime Target location for timestamp taken immediately before
1472d38ceaf9SAlex Deucher * scanout position query. Can be NULL to skip timestamp.
1473d38ceaf9SAlex Deucher * \param *etime Target location for timestamp taken immediately after
1474d38ceaf9SAlex Deucher * scanout position query. Can be NULL to skip timestamp.
1475d38ceaf9SAlex Deucher *
1476d38ceaf9SAlex Deucher * Returns vpos as a positive number while in active scanout area.
1477d38ceaf9SAlex Deucher * Returns vpos as a negative number inside vblank, counting the number
1478d38ceaf9SAlex Deucher * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1479d38ceaf9SAlex Deucher * until start of active scanout / end of vblank."
1480d38ceaf9SAlex Deucher *
1481d38ceaf9SAlex Deucher * \return Flags, or'ed together as follows:
1482d38ceaf9SAlex Deucher *
1483d38ceaf9SAlex Deucher * DRM_SCANOUTPOS_VALID = Query successful.
1484d38ceaf9SAlex Deucher * DRM_SCANOUTPOS_INVBL = Inside vblank.
1485d38ceaf9SAlex Deucher * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1486d38ceaf9SAlex Deucher * this flag means that returned position may be offset by a constant but
1487d38ceaf9SAlex Deucher * unknown small number of scanlines wrt. real scanout position.
1488d38ceaf9SAlex Deucher *
1489d38ceaf9SAlex Deucher */
amdgpu_display_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1490aa8e286aSSamuel Li int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1491aa8e286aSSamuel Li unsigned int pipe, unsigned int flags, int *vpos,
1492aa8e286aSSamuel Li int *hpos, ktime_t *stime, ktime_t *etime,
14933bb403bfSVille Syrjälä const struct drm_display_mode *mode)
1494d38ceaf9SAlex Deucher {
1495d38ceaf9SAlex Deucher u32 vbl = 0, position = 0;
1496d38ceaf9SAlex Deucher int vbl_start, vbl_end, vtotal, ret = 0;
1497d38ceaf9SAlex Deucher bool in_vbl = true;
1498d38ceaf9SAlex Deucher
14991348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
1500d38ceaf9SAlex Deucher
1501d38ceaf9SAlex Deucher /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1502d38ceaf9SAlex Deucher
1503d38ceaf9SAlex Deucher /* Get optional system timestamp before query. */
1504d38ceaf9SAlex Deucher if (stime)
1505d38ceaf9SAlex Deucher *stime = ktime_get();
1506d38ceaf9SAlex Deucher
150788e72717SThierry Reding if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1508d38ceaf9SAlex Deucher ret |= DRM_SCANOUTPOS_VALID;
1509d38ceaf9SAlex Deucher
1510d38ceaf9SAlex Deucher /* Get optional system timestamp after query. */
1511d38ceaf9SAlex Deucher if (etime)
1512d38ceaf9SAlex Deucher *etime = ktime_get();
1513d38ceaf9SAlex Deucher
1514d38ceaf9SAlex Deucher /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1515d38ceaf9SAlex Deucher
1516d38ceaf9SAlex Deucher /* Decode into vertical and horizontal scanout position. */
1517d38ceaf9SAlex Deucher *vpos = position & 0x1fff;
1518d38ceaf9SAlex Deucher *hpos = (position >> 16) & 0x1fff;
1519d38ceaf9SAlex Deucher
1520d38ceaf9SAlex Deucher /* Valid vblank area boundaries from gpu retrieved? */
1521d38ceaf9SAlex Deucher if (vbl > 0) {
1522d38ceaf9SAlex Deucher /* Yes: Decode. */
1523d38ceaf9SAlex Deucher ret |= DRM_SCANOUTPOS_ACCURATE;
1524d38ceaf9SAlex Deucher vbl_start = vbl & 0x1fff;
1525d38ceaf9SAlex Deucher vbl_end = (vbl >> 16) & 0x1fff;
1526b2edaac4SSrinivasan Shanmugam } else {
1527d38ceaf9SAlex Deucher /* No: Fake something reasonable which gives at least ok results. */
15283bb403bfSVille Syrjälä vbl_start = mode->crtc_vdisplay;
1529d38ceaf9SAlex Deucher vbl_end = 0;
1530d38ceaf9SAlex Deucher }
1531d38ceaf9SAlex Deucher
15328e36f9d3SAlex Deucher /* Called from driver internal vblank counter query code? */
15338e36f9d3SAlex Deucher if (flags & GET_DISTANCE_TO_VBLANKSTART) {
15348e36f9d3SAlex Deucher /* Caller wants distance from real vbl_start in *hpos */
15358e36f9d3SAlex Deucher *hpos = *vpos - vbl_start;
15368e36f9d3SAlex Deucher }
15378e36f9d3SAlex Deucher
15388e36f9d3SAlex Deucher /* Fudge vblank to start a few scanlines earlier to handle the
15398e36f9d3SAlex Deucher * problem that vblank irqs fire a few scanlines before start
15408e36f9d3SAlex Deucher * of vblank. Some driver internal callers need the true vblank
15418e36f9d3SAlex Deucher * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
15428e36f9d3SAlex Deucher *
15438e36f9d3SAlex Deucher * The cause of the "early" vblank irq is that the irq is triggered
15448e36f9d3SAlex Deucher * by the line buffer logic when the line buffer read position enters
15458e36f9d3SAlex Deucher * the vblank, whereas our crtc scanout position naturally lags the
15468e36f9d3SAlex Deucher * line buffer read position.
15478e36f9d3SAlex Deucher */
15488e36f9d3SAlex Deucher if (!(flags & USE_REAL_VBLANKSTART))
15498e36f9d3SAlex Deucher vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
15508e36f9d3SAlex Deucher
1551d38ceaf9SAlex Deucher /* Test scanout position against vblank region. */
1552d38ceaf9SAlex Deucher if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1553d38ceaf9SAlex Deucher in_vbl = false;
1554d38ceaf9SAlex Deucher
15558e36f9d3SAlex Deucher /* In vblank? */
15568e36f9d3SAlex Deucher if (in_vbl)
15578e36f9d3SAlex Deucher ret |= DRM_SCANOUTPOS_IN_VBLANK;
15588e36f9d3SAlex Deucher
15598e36f9d3SAlex Deucher /* Called from driver internal vblank counter query code? */
15608e36f9d3SAlex Deucher if (flags & GET_DISTANCE_TO_VBLANKSTART) {
15618e36f9d3SAlex Deucher /* Caller wants distance from fudged earlier vbl_start */
15628e36f9d3SAlex Deucher *vpos -= vbl_start;
15638e36f9d3SAlex Deucher return ret;
15648e36f9d3SAlex Deucher }
15658e36f9d3SAlex Deucher
1566d38ceaf9SAlex Deucher /* Check if inside vblank area and apply corrective offsets:
1567d38ceaf9SAlex Deucher * vpos will then be >=0 in video scanout area, but negative
1568d38ceaf9SAlex Deucher * within vblank area, counting down the number of lines until
1569d38ceaf9SAlex Deucher * start of scanout.
1570d38ceaf9SAlex Deucher */
1571d38ceaf9SAlex Deucher
1572d38ceaf9SAlex Deucher /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1573d38ceaf9SAlex Deucher if (in_vbl && (*vpos >= vbl_start)) {
15743bb403bfSVille Syrjälä vtotal = mode->crtc_vtotal;
1575520f08dfSNicholas Kazlauskas
1576520f08dfSNicholas Kazlauskas /* With variable refresh rate displays the vpos can exceed
1577520f08dfSNicholas Kazlauskas * the vtotal value. Clamp to 0 to return -vbl_end instead
1578520f08dfSNicholas Kazlauskas * of guessing the remaining number of lines until scanout.
1579520f08dfSNicholas Kazlauskas */
1580520f08dfSNicholas Kazlauskas *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1581d38ceaf9SAlex Deucher }
1582d38ceaf9SAlex Deucher
1583d38ceaf9SAlex Deucher /* Correct for shifted end of vbl at vbl_end. */
1584d38ceaf9SAlex Deucher *vpos = *vpos - vbl_end;
1585d38ceaf9SAlex Deucher
1586d38ceaf9SAlex Deucher return ret;
1587d38ceaf9SAlex Deucher }
1588d38ceaf9SAlex Deucher
amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device * adev,int crtc)1589734dd01dSSamuel Li int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1590d38ceaf9SAlex Deucher {
1591d38ceaf9SAlex Deucher if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1592d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_NONE;
1593d38ceaf9SAlex Deucher
1594d38ceaf9SAlex Deucher switch (crtc) {
1595d38ceaf9SAlex Deucher case 0:
1596d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_VBLANK1;
1597d38ceaf9SAlex Deucher case 1:
1598d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_VBLANK2;
1599d38ceaf9SAlex Deucher case 2:
1600d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_VBLANK3;
1601d38ceaf9SAlex Deucher case 3:
1602d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_VBLANK4;
1603d38ceaf9SAlex Deucher case 4:
1604d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_VBLANK5;
1605d38ceaf9SAlex Deucher case 5:
1606d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_VBLANK6;
1607d38ceaf9SAlex Deucher default:
1608d38ceaf9SAlex Deucher return AMDGPU_CRTC_IRQ_NONE;
1609d38ceaf9SAlex Deucher }
1610d38ceaf9SAlex Deucher }
1611ea702333SThomas Zimmermann
amdgpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1612ea702333SThomas Zimmermann bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1613ea702333SThomas Zimmermann bool in_vblank_irq, int *vpos,
1614ea702333SThomas Zimmermann int *hpos, ktime_t *stime, ktime_t *etime,
1615ea702333SThomas Zimmermann const struct drm_display_mode *mode)
1616ea702333SThomas Zimmermann {
1617ea702333SThomas Zimmermann struct drm_device *dev = crtc->dev;
1618ea702333SThomas Zimmermann unsigned int pipe = crtc->index;
1619ea702333SThomas Zimmermann
1620ea702333SThomas Zimmermann return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1621ea702333SThomas Zimmermann stime, etime, mode);
1622ea702333SThomas Zimmermann }
1623a2e15b0eSAlex Deucher
162489e2b437SAlex Deucher static bool
amdgpu_display_robj_is_fb(struct amdgpu_device * adev,struct amdgpu_bo * robj)162589e2b437SAlex Deucher amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
162689e2b437SAlex Deucher {
162789e2b437SAlex Deucher struct drm_device *dev = adev_to_drm(adev);
162889e2b437SAlex Deucher struct drm_fb_helper *fb_helper = dev->fb_helper;
162989e2b437SAlex Deucher
163089e2b437SAlex Deucher if (!fb_helper || !fb_helper->buffer)
163189e2b437SAlex Deucher return false;
163289e2b437SAlex Deucher
163389e2b437SAlex Deucher if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
163489e2b437SAlex Deucher return false;
163589e2b437SAlex Deucher
163689e2b437SAlex Deucher return true;
163789e2b437SAlex Deucher }
163889e2b437SAlex Deucher
amdgpu_display_suspend_helper(struct amdgpu_device * adev)1639a2e15b0eSAlex Deucher int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1640a2e15b0eSAlex Deucher {
1641a2e15b0eSAlex Deucher struct drm_device *dev = adev_to_drm(adev);
1642a2e15b0eSAlex Deucher struct drm_crtc *crtc;
1643a2e15b0eSAlex Deucher struct drm_connector *connector;
1644a2e15b0eSAlex Deucher struct drm_connector_list_iter iter;
1645a2e15b0eSAlex Deucher int r;
1646a2e15b0eSAlex Deucher
1647c69d5139SGuchun Chen drm_kms_helper_poll_disable(dev);
1648c69d5139SGuchun Chen
1649a2e15b0eSAlex Deucher /* turn off display hw */
1650a2e15b0eSAlex Deucher drm_modeset_lock_all(dev);
1651a2e15b0eSAlex Deucher drm_connector_list_iter_begin(dev, &iter);
1652a2e15b0eSAlex Deucher drm_for_each_connector_iter(connector, &iter)
1653a2e15b0eSAlex Deucher drm_helper_connector_dpms(connector,
1654a2e15b0eSAlex Deucher DRM_MODE_DPMS_OFF);
1655a2e15b0eSAlex Deucher drm_connector_list_iter_end(&iter);
1656a2e15b0eSAlex Deucher drm_modeset_unlock_all(dev);
1657a2e15b0eSAlex Deucher /* unpin the front buffers and cursors */
1658a2e15b0eSAlex Deucher list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1659a2e15b0eSAlex Deucher struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1660a2e15b0eSAlex Deucher struct drm_framebuffer *fb = crtc->primary->fb;
1661a2e15b0eSAlex Deucher struct amdgpu_bo *robj;
1662a2e15b0eSAlex Deucher
1663a2e15b0eSAlex Deucher if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1664a2e15b0eSAlex Deucher struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
166593125cb7SSrinivasan Shanmugam
1666a2e15b0eSAlex Deucher r = amdgpu_bo_reserve(aobj, true);
1667a2e15b0eSAlex Deucher if (r == 0) {
1668a2e15b0eSAlex Deucher amdgpu_bo_unpin(aobj);
1669a2e15b0eSAlex Deucher amdgpu_bo_unreserve(aobj);
1670a2e15b0eSAlex Deucher }
1671a2e15b0eSAlex Deucher }
1672a2e15b0eSAlex Deucher
167393125cb7SSrinivasan Shanmugam if (!fb || !fb->obj[0])
1674a2e15b0eSAlex Deucher continue;
167593125cb7SSrinivasan Shanmugam
1676a2e15b0eSAlex Deucher robj = gem_to_amdgpu_bo(fb->obj[0]);
167789e2b437SAlex Deucher if (!amdgpu_display_robj_is_fb(adev, robj)) {
1678a2e15b0eSAlex Deucher r = amdgpu_bo_reserve(robj, true);
1679a2e15b0eSAlex Deucher if (r == 0) {
1680a2e15b0eSAlex Deucher amdgpu_bo_unpin(robj);
1681a2e15b0eSAlex Deucher amdgpu_bo_unreserve(robj);
1682a2e15b0eSAlex Deucher }
1683a2e15b0eSAlex Deucher }
168489e2b437SAlex Deucher }
16854b12ee6fSVictor Zhao return 0;
1686a2e15b0eSAlex Deucher }
1687a2e15b0eSAlex Deucher
amdgpu_display_resume_helper(struct amdgpu_device * adev)1688a2e15b0eSAlex Deucher int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1689a2e15b0eSAlex Deucher {
1690a2e15b0eSAlex Deucher struct drm_device *dev = adev_to_drm(adev);
1691a2e15b0eSAlex Deucher struct drm_connector *connector;
1692a2e15b0eSAlex Deucher struct drm_connector_list_iter iter;
1693a2e15b0eSAlex Deucher struct drm_crtc *crtc;
1694a2e15b0eSAlex Deucher int r;
1695a2e15b0eSAlex Deucher
1696a2e15b0eSAlex Deucher /* pin cursors */
1697a2e15b0eSAlex Deucher list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1698a2e15b0eSAlex Deucher struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1699a2e15b0eSAlex Deucher
1700a2e15b0eSAlex Deucher if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1701a2e15b0eSAlex Deucher struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
170293125cb7SSrinivasan Shanmugam
1703a2e15b0eSAlex Deucher r = amdgpu_bo_reserve(aobj, true);
1704a2e15b0eSAlex Deucher if (r == 0) {
1705a2e15b0eSAlex Deucher r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1706a2e15b0eSAlex Deucher if (r != 0)
1707a2e15b0eSAlex Deucher dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1708a2e15b0eSAlex Deucher amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1709a2e15b0eSAlex Deucher amdgpu_bo_unreserve(aobj);
1710a2e15b0eSAlex Deucher }
1711a2e15b0eSAlex Deucher }
1712a2e15b0eSAlex Deucher }
1713a2e15b0eSAlex Deucher
1714a2e15b0eSAlex Deucher drm_helper_resume_force_mode(dev);
1715a2e15b0eSAlex Deucher
1716a2e15b0eSAlex Deucher /* turn on display hw */
1717a2e15b0eSAlex Deucher drm_modeset_lock_all(dev);
1718a2e15b0eSAlex Deucher
1719a2e15b0eSAlex Deucher drm_connector_list_iter_begin(dev, &iter);
1720a2e15b0eSAlex Deucher drm_for_each_connector_iter(connector, &iter)
1721a2e15b0eSAlex Deucher drm_helper_connector_dpms(connector,
1722a2e15b0eSAlex Deucher DRM_MODE_DPMS_ON);
1723a2e15b0eSAlex Deucher drm_connector_list_iter_end(&iter);
1724a2e15b0eSAlex Deucher
1725a2e15b0eSAlex Deucher drm_modeset_unlock_all(dev);
1726a2e15b0eSAlex Deucher
1727c69d5139SGuchun Chen drm_kms_helper_poll_enable(dev);
1728c69d5139SGuchun Chen
1729a2e15b0eSAlex Deucher return 0;
1730a2e15b0eSAlex Deucher }
1731a2e15b0eSAlex Deucher
1732