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Searched refs:gate (Results 1 – 25 of 64) sorted by relevance

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/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_sunxi.c25 const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id); in sunxi_set_gate() local
28 if (!(gate->flags & CCU_CLK_F_IS_VALID)) { in sunxi_set_gate()
34 clk->id, gate->off, ilog2(gate->bit)); in sunxi_set_gate()
36 reg = readl(priv->base + gate->off); in sunxi_set_gate()
38 reg |= gate->bit; in sunxi_set_gate()
40 reg &= ~gate->bit; in sunxi_set_gate()
42 writel(reg, priv->base + gate->off); in sunxi_set_gate()
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga.dtsi300 compatible = "altr,socfpga-gate-clk";
302 clk-gate = <0x60 0>;
314 compatible = "altr,socfpga-gate-clk";
317 clk-gate = <0x60 1>;
322 compatible = "altr,socfpga-gate-clk";
329 compatible = "altr,socfpga-gate-clk";
332 clk-gate = <0x60 2>;
337 compatible = "altr,socfpga-gate-clk";
340 clk-gate = <0x60 3>;
345 compatible = "altr,socfpga-gate-clk";
[all …]
H A Dam35xx-clocks.dtsi13 compatible = "ti,am35xx-gate-clock";
21 compatible = "ti,gate-clock";
29 compatible = "ti,am35xx-gate-clock";
37 compatible = "ti,gate-clock";
45 compatible = "ti,am35xx-gate-clock";
53 compatible = "ti,gate-clock";
61 compatible = "ti,am35xx-gate-clock";
98 compatible = "ti,wait-gate-clock";
H A Domap36xx-clocks.dtsi20 compatible = "ti,hsdiv-gate-clock";
30 compatible = "ti,hsdiv-gate-clock";
39 compatible = "ti,hsdiv-gate-clock";
48 compatible = "ti,hsdiv-gate-clock";
57 compatible = "ti,hsdiv-gate-clock";
66 compatible = "ti,wait-gate-clock";
H A Domap3xxx-clocks.dtsi36 compatible = "ti,gate-clock";
222 compatible = "ti,gate-clock";
264 compatible = "ti,gate-clock";
379 compatible = "ti,gate-clock";
438 compatible = "ti,gate-clock";
466 compatible = "ti,gate-clock";
494 compatible = "ti,gate-clock";
511 compatible = "ti,composite-no-wait-gate-clock";
595 compatible = "ti,composite-gate-clock";
617 compatible = "ti,composite-gate-clock";
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi48 compatible = "ti,composite-gate-clock";
109 compatible = "ti,wait-gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,dss-gate-clock";
182 compatible = "ti,gate-clock";
190 compatible = "ti,dss-gate-clock";
H A Dam43xx-clocks.dtsi109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,gate-clock";
141 compatible = "ti,gate-clock";
149 compatible = "ti,gate-clock";
351 compatible = "ti,gate-clock";
504 compatible = "ti,gate-clock";
512 compatible = "ti,gate-clock";
520 compatible = "ti,gate-clock";
[all …]
H A Dsocfpga_arria10.dtsi353 compatible = "altr,socfpga-a10-gate-clk";
356 clk-gate = <0x48 1>;
361 compatible = "altr,socfpga-a10-gate-clk";
364 clk-gate = <0x48 2>;
369 compatible = "altr,socfpga-a10-gate-clk";
372 clk-gate = <0x48 3>;
377 compatible = "altr,socfpga-a10-gate-clk";
380 clk-gate = <0x48 0>;
385 compatible = "altr,socfpga-a10-gate-clk";
387 clk-gate = <0xC8 5>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi53 compatible = "ti,gate-clock";
70 compatible = "ti,gate-clock";
134 compatible = "ti,wait-gate-clock";
142 compatible = "ti,wait-gate-clock";
187 compatible = "ti,wait-gate-clock";
219 compatible = "ti,wait-gate-clock";
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
27 Example using multiple gate clocks:
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
390 struct bcm_clk_gate gate; member
394 struct bcm_clk_gate gate; member
398 struct bcm_clk_gate gate; member
H A Dclk-bcm235xx.c131 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
H A Dclk-core.c83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
105 if (gate_exists(gate)) { in peri_clk_enable()
106 reg = readl(base + cd->gate.offset); in peri_clk_enable()
107 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
108 writel(reg, base + cd->gate.offset); in peri_clk_enable()
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
145 reg = readl(base + cd->gate.offset); in peri_clk_enable()
146 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
147 writel(reg, base + cd->gate.offset); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
390 struct bcm_clk_gate gate; member
394 struct bcm_clk_gate gate; member
398 struct bcm_clk_gate gate; member
H A Dclk-bcm281xx.c131 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
H A Dclk-core.c83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
105 if (gate_exists(gate)) { in peri_clk_enable()
106 reg = readl(base + cd->gate.offset); in peri_clk_enable()
107 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
108 writel(reg, base + cd->gate.offset); in peri_clk_enable()
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
145 reg = readl(base + cd->gate.offset); in peri_clk_enable()
146 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
147 writel(reg, base + cd->gate.offset); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c386 const struct mtk_gate *gate = &priv->gates[clk->id]; in mtk_clk_gate_enable() local
387 u32 bit = BIT(gate->shift); in mtk_clk_gate_enable()
389 switch (gate->flags & CLK_GATE_MASK) { in mtk_clk_gate_enable()
391 writel(bit, priv->base + gate->regs->clr_ofs); in mtk_clk_gate_enable()
394 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); in mtk_clk_gate_enable()
407 const struct mtk_gate *gate = &priv->gates[clk->id]; in mtk_clk_gate_disable() local
408 u32 bit = BIT(gate->shift); in mtk_clk_gate_disable()
410 switch (gate->flags & CLK_GATE_MASK) { in mtk_clk_gate_disable()
412 writel(bit, priv->base + gate->regs->set_ofs); in mtk_clk_gate_disable()
415 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); in mtk_clk_gate_disable()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c169 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
173 gate = SCG_PLL_PFD0_GATE_MASK; in scg_apll_pfd_get_rate()
179 gate = SCG_PLL_PFD1_GATE_MASK; in scg_apll_pfd_get_rate()
185 gate = SCG_PLL_PFD2_GATE_MASK; in scg_apll_pfd_get_rate()
191 gate = SCG_PLL_PFD3_GATE_MASK; in scg_apll_pfd_get_rate()
201 if (reg & gate || !(reg & valid)) in scg_apll_pfd_get_rate()
219 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
223 gate = SCG_PLL_PFD0_GATE_MASK; in scg_spll_pfd_get_rate()
229 gate = SCG_PLL_PFD1_GATE_MASK; in scg_spll_pfd_get_rate()
235 gate = SCG_PLL_PFD2_GATE_MASK; in scg_spll_pfd_get_rate()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Drdc-sema.c66 &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
67 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
94 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
98 writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
/openbmc/u-boot/drivers/clk/
H A Dclk_meson_axg.c54 struct meson_gate *gate; in meson_set_gate() local
59 gate = &gates[clk->id]; in meson_set_gate()
61 if (gate->reg == 0) in meson_set_gate()
64 regmap_update_bits(priv->map, gate->reg, in meson_set_gate()
65 BIT(gate->bit), on ? BIT(gate->bit) : 0); in meson_set_gate()
H A Dclk_stm32mp1.c405 const struct stm32mp1_clk_gate *gate; member
731 .gate = stm32mp1_clk_gate,
752 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_id() local
756 if (gate[i].index == id) in stm32mp1_clk_get_id()
771 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_sel() local
773 if (gate[i].sel > _PARENT_SEL_NB) { in stm32mp1_clk_get_sel()
779 return gate[i].sel; in stm32mp1_clk_get_sel()
785 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_fixed_parent() local
787 if (gate[i].fixed == _UNKNOWN_ID) in stm32mp1_clk_get_fixed_parent()
790 return gate[i].fixed; in stm32mp1_clk_get_fixed_parent()
[all …]
/openbmc/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier-core.c29 const struct uniphier_clk_gate_data *gate) in uniphier_clk_gate_enable() argument
33 val = readl(priv->base + gate->reg); in uniphier_clk_gate_enable()
34 val |= BIT(gate->bit); in uniphier_clk_gate_enable()
35 writel(val, priv->base + gate->reg); in uniphier_clk_gate_enable()
99 parent_id = data->data.gate.parent_id; in uniphier_clk_get_parent_data()
124 uniphier_clk_gate_enable(priv, &data->data.gate); in __uniphier_clk_enable()
H A Dclk-uniphier.h45 struct uniphier_clk_gate_data gate; member
63 .data.gate = { \
/openbmc/qemu/hw/i386/kvm/
H A Di8254.c120 sc->gate = kchan->gate; in kvm_pit_get()
157 kchan->gate = sc->gate; in kvm_pit_put()
183 if (sc->gate < val) { in kvm_pit_set_gate()
189 sc->gate = val; in kvm_pit_set_gate()
/openbmc/qemu/target/i386/hvf/
H A Dx86.c103 int gate) in x86_read_call_gate() argument
109 if (gate * 8 >= limit) { in x86_read_call_gate()
114 vmx_read_mem(cpu, idt_desc, base + gate * 8, sizeof(*idt_desc)); in x86_read_call_gate()

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