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Searched refs:feature_mask (Results 1 – 25 of 56) sorted by relevance

123

/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c589 uint64_t *feature_mask) in smu_cmn_get_enabled_mask() argument
595 if (!feature_mask) in smu_cmn_get_enabled_mask()
598 feature_mask_low = &((uint32_t *)feature_mask)[0]; in smu_cmn_get_enabled_mask()
599 feature_mask_high = &((uint32_t *)feature_mask)[1]; in smu_cmn_get_enabled_mask()
645 uint64_t feature_mask, in smu_cmn_feature_update_enable_state() argument
653 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
659 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
664 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
670 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
712 uint64_t feature_mask; in smu_cmn_get_pp_feature_mask() local
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H A Dsmu_cmn.h75 uint64_t *feature_mask);
82 uint64_t feature_mask,
H A Dsmu_internal.h75 …e smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0,… argument
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr.c102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
123 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
136 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
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H A Dvega20_hwmgr.c103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data()
106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data()
109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data()
112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data()
115 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) in vega20_set_default_registry_data()
118 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data()
121 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) in vega20_set_default_registry_data()
173 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); in vega20_set_default_registry_data()
1820 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) in vega20_upload_dpm_min_level() argument
1828 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in vega20_upload_dpm_min_level()
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H A Dvega10_hwmgr.c120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; in vega10_set_default_registry_data()
153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data()
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/openbmc/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_device.c319 kernel_ulong_t feature_mask) in proc_thermal_mmio_add() argument
323 proc_priv->mmio_feature_mask = feature_mask; in proc_thermal_mmio_add()
325 if (feature_mask) { in proc_thermal_mmio_add()
331 if (feature_mask & PROC_THERMAL_FEATURE_RAPL) { in proc_thermal_mmio_add()
339 if (feature_mask & PROC_THERMAL_FEATURE_FIVR || in proc_thermal_mmio_add()
340 feature_mask & PROC_THERMAL_FEATURE_DVFS || in proc_thermal_mmio_add()
341 feature_mask & PROC_THERMAL_FEATURE_DLVR) { in proc_thermal_mmio_add()
349 if (feature_mask & PROC_THERMAL_FEATURE_MBOX) { in proc_thermal_mmio_add()
H A Dprocessor_thermal_device.h94 kernel_ulong_t feature_mask);
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c258 uint32_t *feature_mask, uint32_t num) in smu_v13_0_7_get_allowed_feature_mask() argument
265 memset(feature_mask, 0, sizeof(uint32_t) * num); in smu_v13_0_7_get_allowed_feature_mask()
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); in smu_v13_0_7_get_allowed_feature_mask()
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_7_get_allowed_feature_mask()
272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); in smu_v13_0_7_get_allowed_feature_mask()
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_7_get_allowed_feature_mask()
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v13_0_7_get_allowed_feature_mask()
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H A Dsmu_v13_0_0_ppt.c289 uint32_t *feature_mask, uint32_t num) in smu_v13_0_0_get_allowed_feature_mask() argument
297 memset(feature_mask, 0xff, sizeof(uint32_t) * num); in smu_v13_0_0_get_allowed_feature_mask()
300 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
301 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_0_get_allowed_feature_mask()
306 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); in smu_v13_0_0_get_allowed_feature_mask()
309 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
315 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_0_get_allowed_feature_mask()
318 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v13_0_0_get_allowed_feature_mask()
320 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); in smu_v13_0_0_get_allowed_feature_mask()
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H A Dsmu_v13_0_6_ppt.c287 uint32_t *feature_mask, in smu_v13_0_6_get_allowed_feature_mask() argument
294 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in smu_v13_0_6_get_allowed_feature_mask()
1007 uint32_t feature_mask, uint32_t level) in smu_v13_0_6_upload_dpm_level() argument
1014 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) { in smu_v13_0_6_upload_dpm_level()
1030 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) { in smu_v13_0_6_upload_dpm_level()
1047 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) { in smu_v13_0_6_upload_dpm_level()
1645 uint64_t *feature_mask) in smu_v13_0_6_get_enabled_mask() argument
1651 ret = smu_cmn_get_enabled_mask(smu, feature_mask); in smu_v13_0_6_get_enabled_mask()
1654 *feature_mask = 0; in smu_v13_0_6_get_enabled_mask()
/openbmc/linux/drivers/mfd/
H A Dkempld-core.c67 pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE); in kempld_get_info_generic()
69 pld->feature_mask = 0; in kempld_get_info_generic()
97 if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C) in kempld_register_cells_generic()
100 if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG) in kempld_register_cells_generic()
103 if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO) in kempld_register_cells_generic()
106 if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART) in kempld_register_cells_generic()
/openbmc/linux/drivers/pci/msi/
H A Dirqdomain.c324 bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask, in pci_msi_domain_supports() argument
358 return (supported & feature_mask) == feature_mask; in pci_msi_domain_supports()
H A Dmsi.h109 bool pci_msi_domain_supports(struct pci_dev *dev, unsigned int feature_mask, enum support_mode mode…
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
H A Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
H A Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
H A Dvega12_smumgr.c126 bool enable, uint64_t feature_mask) in vega12_enable_smc_features() argument
130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega12_enable_smc_features()
131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega12_enable_smc_features()
H A Dvega20_smumgr.c318 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument
323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features()
324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c566 uint64_t *feature_mask) in cyan_skillfish_get_enabled_mask() argument
568 if (!feature_mask) in cyan_skillfish_get_enabled_mask()
570 memset(feature_mask, 0xff, sizeof(*feature_mask)); in cyan_skillfish_get_enabled_mask()
H A Dnavi10_ppt.c279 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask() argument
286 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask()
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) in navi10_get_allowed_feature_mask()
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in navi10_get_allowed_feature_mask()
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); in navi10_get_allowed_feature_mask()
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in navi10_get_allowed_feature_mask()
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask()
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); in navi10_get_allowed_feature_mask()
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/openbmc/linux/drivers/net/
H A Dtap.c956 netdev_features_t feature_mask = 0; in set_offload() local
965 feature_mask = NETIF_F_HW_CSUM; in set_offload()
969 feature_mask |= NETIF_F_TSO_ECN; in set_offload()
971 feature_mask |= NETIF_F_TSO; in set_offload()
973 feature_mask |= NETIF_F_TSO6; in set_offload()
989 if (feature_mask & (NETIF_F_TSO | NETIF_F_TSO6) || in set_offload()
990 (feature_mask & (TUN_F_USO4 | TUN_F_USO6)) == (TUN_F_USO4 | TUN_F_USO6)) in set_offload()
998 tap->tap_features = feature_mask; in set_offload()
/openbmc/linux/arch/x86/mm/
H A Dmem_encrypt_identity.c496 unsigned long feature_mask; in sme_enable() local
532 feature_mask = (msr & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT; in sme_enable()
539 if (feature_mask == AMD_SME_BIT) { in sme_enable()
/openbmc/linux/include/sound/sof/
H A Dext_manifest4.h74 uint32_t feature_mask; member
/openbmc/linux/include/linux/mfd/
H A Dkempld.h91 u32 feature_mask; member

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