1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2018 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan #ifndef _VEGA20_SMUMANAGER_H_ 24e098bc96SEvan Quan #define _VEGA20_SMUMANAGER_H_ 25e098bc96SEvan Quan 26e098bc96SEvan Quan #include "hwmgr.h" 27e098bc96SEvan Quan #include "smu11_driver_if.h" 28e098bc96SEvan Quan 29e098bc96SEvan Quan struct smu_table_entry { 30e098bc96SEvan Quan uint32_t version; 31e098bc96SEvan Quan uint32_t size; 32e098bc96SEvan Quan uint64_t mc_addr; 33e098bc96SEvan Quan void *table; 34e098bc96SEvan Quan struct amdgpu_bo *handle; 35e098bc96SEvan Quan }; 36e098bc96SEvan Quan 37e098bc96SEvan Quan struct smu_table_array { 38e098bc96SEvan Quan struct smu_table_entry entry[TABLE_COUNT]; 39e098bc96SEvan Quan }; 40e098bc96SEvan Quan 41e098bc96SEvan Quan struct vega20_smumgr { 42e098bc96SEvan Quan struct smu_table_array smu_tables; 43e098bc96SEvan Quan }; 44e098bc96SEvan Quan 45e098bc96SEvan Quan #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF 46e098bc96SEvan Quan #define SMU_FEATURES_LOW_SHIFT 0 47e098bc96SEvan Quan #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 48e098bc96SEvan Quan #define SMU_FEATURES_HIGH_SHIFT 32 49e098bc96SEvan Quan 50e098bc96SEvan Quan int vega20_enable_smc_features(struct pp_hwmgr *hwmgr, 51e098bc96SEvan Quan bool enable, uint64_t feature_mask); 52e098bc96SEvan Quan int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr, 53e098bc96SEvan Quan uint64_t *features_enabled); 54e098bc96SEvan Quan int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr, 55e098bc96SEvan Quan uint8_t *table, uint16_t workload_type); 56e098bc96SEvan Quan int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr, 57e098bc96SEvan Quan uint8_t *table, uint16_t workload_type); 58e098bc96SEvan Quan int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr); 59e098bc96SEvan Quan 60e098bc96SEvan Quan bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr); 61e098bc96SEvan Quan 62e098bc96SEvan Quan #endif 63e098bc96SEvan Quan 64