| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | wrpll-cln28hpc.c | 247 u8 fbdiv, divq, best_r, r; in analogbits_wrpll_configure_for_rate() local
296 fbdiv = __wrpll_calc_fbdiv(c); in analogbits_wrpll_configure_for_rate()
309 f >>= (fbdiv - 1); in analogbits_wrpll_configure_for_rate()
312 vco_pre = fbdiv * post_divr_freq; in analogbits_wrpll_configure_for_rate()
361 u8 fbdiv; in analogbits_wrpll_calc_output_rate() local
367 fbdiv = __wrpll_calc_fbdiv(c); in analogbits_wrpll_calc_output_rate()
368 n = parent_rate * fbdiv * (c->divf + 1); in analogbits_wrpll_calc_output_rate()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
78 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config() local
114 fbdiv = vco_khz / fref_khz; in pll_para_config()
115 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) in pll_para_config()
117 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
118 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { in pll_para_config()
119 fbdiv++; in pll_para_config()
[all …]
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| H A D | clk_rk3399.c | 34 u32 fbdiv; member
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
322 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
326 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
340 div->fbdiv << PLL_FBDIV_SHIFT); in rkclk_set_pll()
359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
395 fbdiv = vco_khz / fref_khz; in pll_para_config()
396 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) in pll_para_config()
398 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
[all …]
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| H A D | clk_rk322x.c | 30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
200 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
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| H A D | clk_rk3036.c | 33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
66 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
199 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rk3328.c | 22 u32 fbdiv; member
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
264 (div->fbdiv << PLL_FBDIV_SHIFT) | in rkclk_set_pll()
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| H A D | clk_rv1108.c | 33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
131 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk_mipi.c | 202 u64 fbdiv; in rk_mipi_phy_enable() local
280 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
281 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
285 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
290 test_data[0] = (fbdiv - 1) & 0x1f; in rk_mipi_phy_enable()
292 test_data[0] = (fbdiv - 1) >> 5 | 0x80; in rk_mipi_phy_enable()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk-hsdk-cgu.c | 185 u32 fbdiv; member
350 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
373 u32 idiv, fbdiv, odiv; in pll_get() local
391 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in pll_get()
395 rate = (u64)PARENT_RATE * fbdiv; in pll_get()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3036.h | 62 u32 fbdiv; member
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| H A D | cru_rk322x.h | 63 u32 fbdiv; member
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| H A D | cru_rk3128.h | 65 u32 fbdiv; member
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| H A D | cru_rv1108.h | 55 u32 fbdiv; member
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 341 dpll_init_cfg.fbdiv); in rkdclk_init()
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