| /openbmc/qemu/target/hexagon/mmvec/ |
| H A D | macros.h | 309 #define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V)))
312 fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V))
316 fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V))
320 ((fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V)) >> 1)
322 ((fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
324 ((fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V)) >> 1)
326 fVSATUN(WIDTH, ((fZXTN(WIDTH, 2 * WIDTH, U) - \
327 fZXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1))
344 (((fZXTN(32, 64, A) + fZXTN(32, 64, B) + C) >> 32) & 1)
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| /openbmc/qemu/target/hexagon/imported/mmvec/ |
| H A D | macros.def | 740 fVSATW( ( ( ((long long)U)<<32 ) | fZXTN(32,64,V) ) ),
750 fVSATUN( WIDTH, fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V)),
760 fVSATUN( WIDTH, fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V)),
770 ((fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V))>>1),
775 ((fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V)+1)>>1),
780 ((fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V))>>1),
785 fVSATUN(WIDTH,((fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V)+1)>>1)),
830 (((fZXTN(32,64,A)+fZXTN(32,64,B)+C) >> 32) & 1),
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | shift.idef | 210 { RddV = fASHIFTL(RttV,uiV*8,8_8) | fZXTN(uiV*8,64,RssV); })
214 { RddV = fASHIFTL(RttV,(PuV&7)*8,8_8) | fZXTN((PuV&7)*8,64,RssV); })
303 fSETWORD(0,RddV,fZXTN(uiV,32,RsV));
309 fHIDE(size4u_t) shamt = fZXTN(5,32,RtV);
311 fSETWORD(0,RddV,fZXTN(shamt,32,RsV));
331 RdV = fZXTN(width,32,(fCAST4_4u(RsV) >> offset));
360 RddV = fZXTN(width,64,(fCAST8_8u(RssV) >> offset));
379 fHIDE(int) width=fZXTN(6,32,(fGETWORD(1,RttV)));
396 fHIDE(int) width=fZXTN(6,32,(fGETWORD(1,RttV)));
406 fHIDE(int) width=fZXTN(6,32,(fGETWORD(1,RttV)));
[all …]
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| H A D | macros.def | 79 (fZXTN(WIDTH,32,(INREG >> OFFSET))),
85 (fZXTN(WIDTH,32,fBIDIR_LSHIFTR((INREG),(OFFSET),4_8))),
91 (fZXTN((HIBIT-LOWBIT+1),32,(INREG >> LOWBIT))),
204 fZXTN, /* macro name */
211 ((fZXTN(N,M,VAL) ^ (1LL<<((N)-1))) - (1LL<<((N)-1))),
256 ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATUVALN(N,VAL)),
262 ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATUVALN(N,VAL)),
792 (fSE32_64(A)*fZXTN(16,64,B)), /* behavior */
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| H A D | alu.idef | 49 COND_ALU(A4_pzxtb,"Rd32=zxtb(Rs32)","Conditionally zero-extend byte", RdV=fZXTN(8,32,RsV))
51 COND_ALU(A4_pzxth,"Rd32=zxth(Rs32)","Conditionally zero-extend halfword", RdV=fZXTN(16,32,RsV))
261 "Zero extend half", {RdV = fZXTN(16,32,RsV);})
1067 fSETWORD(i,RddV,(fZXTN(32,33,fGETUWORD(i,RssV))+fZXTN(32,33,fGETUWORD(i,RttV)))>>1);
1076 fSETWORD(i,RddV,(fZXTN(32,33,fGETUWORD(i,RssV))+fZXTN(32,33,fGETUWORD(i,RttV))+1)>>1);
1120 …d_rr,"Rd32=round(Rs32,Rt32)",ATTRIBS(),"Round", {RdV = fRNDN(RsV,fZXTN(5,32,RtV))>>fZXTN(5,32,RtV)…
1122 …round(Rs32,Rt32):sat",ATTRIBS(),"Round", {RdV = (fSAT(fRNDN(RsV,fZXTN(5,32,RtV))))>>fZXTN(5,32,RtV…
1126 Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV = fCRNDN(RsV,fZXTN(…
1159 CROUND(RddV,RssV,fZXTN(6,32,RtV));
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| H A D | subinsns.idef | 43 Q6INSN(SA1_zxtb, "Rd16=and(Rs16,#255)", ATTRIBS(A_SUBINSN),"Zxtb", { RdV= fZXTN(8,32,Rs…
46 Q6INSN(SA1_zxth, "Rd16=zxth(Rs16)", ATTRIBS(A_SUBINSN),"Zxth", { RdV= fZXTN(16,32,R…
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| H A D | float.idef | 244 RxxV += (fGETUWORD(0,RssV) * (0x00100000 | fZXTN(20,64,fGETUWORD(1,RttV)))) << 1;
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| H A D | compare.idef | 592 "Transfer predicate to general register", { RdV = fZXTN(8,32,PsV); })
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| /openbmc/qemu/target/hexagon/ |
| H A D | macros.h | 204 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
271 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) macro
300 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
302 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
406 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
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| H A D | decode.c | 27 #define fZXTN(N, M, VAL) ((VAL) & ((1LL << (N)) - 1)) macro
385 pkt->insn[i].immed[immed_num] = extender | fZXTN(6, 32, base_immed); in apply_extender()
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| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | macros.h.inc | 31 #define fCAST2_8u(A) fZXTN(16, 64, A)
85 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
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| H A D | idef-parser.lex | 168 "fZXTN" { return ZXT; }
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