Searched refs:fMPY32SU (Results 1 – 5 of 5) sorted by relevance
| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | idef-parser.lex | 280 "fMPY32SU" { yylval->mpy.first_bit_width = 32;
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| /openbmc/qemu/target/hexagon/ |
| H A D | macros.h | 404 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) macro
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | macros.def | 779 fMPY32SU, /* multiply half integer */
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| H A D | mpy.idef | 110 Q6INSN(M2_mpysu_up, "Rd32=mpysu(Rs32,Rt32)", ATTRIBS(),"Multiply 32x32",{RdV=fMPY32SU(RsV,fCAS…
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| /openbmc/qemu/target/hexagon/imported/mmvec/ |
| H A D | ext.idef | 1433 prod = fMPY32SU(VuV.w[i],fGETUHALF(0,VvV.w[i]));
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