| /openbmc/qemu/target/hexagon/imported/ |
| H A D | branch.idef | 32 {fIMMEXT(riV); fPCALIGN(riV); fBRANCH(fREAD_PC()+riV,COF_TYPE_JUMP);})
47 fIMMEXT(riV);fPCALIGN(riV); fBRANCH(fREAD_PC()+riV,COF_TYPE_JUMP);)
59 fIMMEXT(riV); fPCALIGN(riV); fBRANCH(fREAD_PC()+riV,COF_TYPE_JUMPNEW);)
106 …ANCH_SPECULATE_STALL(fLSBNEW0,,SPECULATE_NOT_TAKEN,13,0) if (fLSBNEW0) {fIMMEXT(riV); fPCALIGN(ri…
107 …SPECULATE_STALL(fLSBNEW0NOT,,SPECULATE_NOT_TAKEN,13,0) if (fLSBNEW0NOT) {fIMMEXT(riV); fPCALIGN(ri…
108 …ANCH_SPECULATE_STALL(fLSBNEW0,,SPECULATE_TAKEN,13,0) if (fLSBNEW0) {fIMMEXT(riV); fPCALIGN(ri…
109 …SPECULATE_STALL(fLSBNEW0NOT,,SPECULATE_TAKEN,13,0) if (fLSBNEW0NOT) {fIMMEXT(riV); fPCALIGN(ri…
110 …ANCH_SPECULATE_STALL(fLSBNEW1,,SPECULATE_NOT_TAKEN,13,0) if (fLSBNEW1) {fIMMEXT(riV); fPCALIGN(ri…
111 …SPECULATE_STALL(fLSBNEW1NOT,,SPECULATE_NOT_TAKEN,13,0) if (fLSBNEW1NOT) {fIMMEXT(riV); fPCALIGN(ri…
112 …ANCH_SPECULATE_STALL(fLSBNEW1,,SPECULATE_TAKEN,13,0) if (fLSBNEW1) {fIMMEXT(riV); fPCALIGN(ri…
[all …]
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| H A D | compare.idef | 62 {fIMMEXT(siV); RdV=(RsV==siV); })
66 {fIMMEXT(siV); RdV=(RsV!=siV); })
109 {fIMMEXT(siV); PdV=f8BITSOF(RsV==siV);})
113 {fIMMEXT(siV); PdV=f8BITSOF(RsV>siV);})
117 {fIMMEXT(uiV); PdV=f8BITSOF(fCAST4u(RsV)>fCAST4u(uiV));})
130 Q6INSN(C4_cmpneqi,"Pd4=!cmp.eq(Rs32,#s10)",ATTRIBS(), "Compare for Not Equal", {fIMMEXT(siV); PdV=f…
131 Q6INSN(C4_cmpltei,"Pd4=!cmp.gt(Rs32,#s10)",ATTRIBS(), "Compare for Less Than or Equal", {fIMMEXT(si…
132 …mp.gtu(Rs32,#u9)",ATTRIBS(), "Compare for Less Than or Equal Unsigned", {fIMMEXT(uiV); PdV=f8BITSO…
220 { fIMMEXT(siV); if (fLSBNEW(PuN)) RdV=siV; else CANCEL;})
224 { fIMMEXT(siV); if (fLSBNEWNOT(PuN)) RdV=siV; else CANCEL;})
[all …]
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| H A D | ldst.idef | 24 Q6INSN(L2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")", ATTRIB,DESCR,{fIMMEXT(siV); fEA_RI(RsV,si…
105 Q6INSN(S2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")="DEST, ATTRIB,DESCR,{fIMMEXT(siV); fEA_RI(RsV,si…
221 Q6INSN(L2_p##TAG##t_io, "if (Pt4) "OPER"(Rs32+#u6:"SHFT")", ATTRIB,DESCR,{fIMMEXT(uiV); …
223 Q6INSN(L2_p##TAG##f_io, "if (!Pt4) "OPER"(Rs32+#u6:"SHFT")", ATTRIB,DESCR,{fIMMEXT(uiV); …
225 Q6INSN(L2_p##TAG##tnew_io,"if (Pt4.new) "OPER"(Rs32+#u6:"SHFT")",ATTRIB,DESCR,{fIMMEXT(uiV); fEA_RI…
226 Q6INSN(L2_p##TAG##fnew_io,"if (!Pt4.new) "OPER"(Rs32+#u6:"SHFT")",ATTRIB,DESCR,{fIMMEXT(uiV); fEA_R…
251 Q6INSN(S2_p##TAG##t_io, "if (Pv4) "OPER"(Rs32+#u6:"SHFT")="DEST, ATTRIB,DESCR,{fIMMEXT(uiV); fE…
253 Q6INSN(S2_p##TAG##f_io, "if (!Pv4) "OPER"(Rs32+#u6:"SHFT")="DEST, ATTRIB,DESCR,{fIMMEXT(uiV); f…
257 Q6INSN(S4_p##TAG##tnew_io,"if (Pv4.new) "OPER"(Rs32+#u6:"SHFT")="DEST,ATTRIB,DESCR,{fIMMEXT(uiV); f…
258 Q6INSN(S4_p##TAG##fnew_io,"if (!Pv4.new) "OPER"(Rs32+#u6:"SHFT")="DEST,ATTRIB,DESCR,{fIMMEXT(uiV); …
[all …]
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| H A D | alu.idef | 43 COND_ALU(A2_paddi,"Rd32=add(Rs32,#s8)","Conditionally Add Register and immediate",fIMMEXT(siV); RdV…
67 { fIMMEXT(siV); RdV=RsV+siV;})
72 { RdV=fREAD_PC()+fIMMEXT(uiV);})
255 "transfer signed immediate to register",{ fIMMEXT(siV); RdV=siV;})
274 { fIMMEXT(siV); fSETWORD(0,RddV,siV);
280 { fIMMEXT(siV); fSETWORD(0,RddV,RsV);
288 { fIMMEXT(siV); fSETWORD(0,RddV,SiV); fSETWORD(1,RddV,siV); })
291 { fIMMEXT(UiV); fSETWORD(0,RddV,UiV); fSETWORD(1,RddV,siV); })
368 { RdV = RsV + RuV + fIMMEXT(siV); })
373 { RdV = RsV - RuV + fIMMEXT(siV); })
[all …]
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| H A D | subinsns.idef | 30 Q6INSN(SA1_addi, "Rx16=add(Rx16,#s7)", ATTRIBS(A_SUBINSN),"Add", { fIMMEXT(siV); RxV=…
32 Q6INSN(SA1_seti, "Rd16=#u6", ATTRIBS(A_SUBINSN),"Set immed", { fIMMEXT(uiV); RdV=…
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| H A D | mpy.idef | 76 { fIMMEXT(uiV); RdV=RsV*uiV; })
84 { fIMMEXT(uiV); RxV=RxV + (RsV*uiV);})
88 { fIMMEXT(uiV); RxV=RxV - (RsV*uiV);})
141 { fIMMEXT(siV); RxV=RxV + RsV + siV;})
149 { fIMMEXT(siV); RxV=RxV - (RsV + siV);})
168 { fIMMEXT(uiV); RdV = RuV + RsV*uiV;})
174 { fIMMEXT(uiV); RdV = uiV + RsV*UiV;})
180 { fIMMEXT(uiV); RdV = uiV + RsV*RtV;})
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| H A D | shift.idef | 185 Q6INSN(S4_andi_##TAGEND,"Rx32=and(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)&INNERSEM;})\
186 Q6INSN(S4_ori_##TAGEND, "Rx32=or(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)|INNERSEM;})\
187 Q6INSN(S4_addi_##TAGEND,"Rx32=add(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)+INNERSEM;})\
188 Q6INSN(S4_subi_##TAGEND,"Rx32=sub(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)-INNERSEM;})
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| H A D | macros.def | 323 fIMMEXT,
330 fIMMEXT(IMM),
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| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | idef-parser.lex | 302 "fIMMEXT" |
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| /openbmc/qemu/target/hexagon/ |
| H A D | macros.h | 311 #define fIMMEXT(IMM) (IMM = IMM) macro
312 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
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| H A D | genptr.c | 548 fIMMEXT(riV); in gen_loop0r()
562 fIMMEXT(riV); in gen_loop1r()
575 fIMMEXT(riV); in gen_ploopNsr()
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