Searched refs:fEA_IRs (Results 1 – 5 of 5) sorted by relevance
/openbmc/qemu/target/hexagon/ |
H A D | gen_tcg.h | 173 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false) 177 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true) 225 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false) 229 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true) 272 fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV)) 303 fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV))
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H A D | macros.h | 433 #define fEA_IRs(IMM, REG, SCALE) \ macro 447 #define fEA_IRs(IMM, REG, SCALE) \ macro
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/openbmc/qemu/target/hexagon/idef-parser/ |
H A D | macros.h.inc | 109 #define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE))
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/openbmc/qemu/target/hexagon/imported/ |
H A D | ldst.idef | 25 Q6INSN(L4_##TAG##_ur, OPER"(Rt32<<#u2+#U6)", ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IRs(… 109 … OPER"(Ru32<<#u2+#U6)="DEST, ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IRs(UiV,RuV,uiV); SEM…
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H A D | macros.def | 881 fEA_IRs, /* Calculate EA with Immediate + Registers scaled Offset */
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