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Searched refs:etsec (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/net/fsl_etsec/
H A Drings.c106 static void read_buffer_descriptor(eTSEC *etsec, in read_buffer_descriptor() argument
117 if (etsec->regs[DMACTRL].value & DMACTRL_LE) { in read_buffer_descriptor()
128 static void write_buffer_descriptor(eTSEC *etsec, in write_buffer_descriptor() argument
134 if (etsec->regs[DMACTRL].value & DMACTRL_LE) { in write_buffer_descriptor()
150 static void ievent_set(eTSEC *etsec, in ievent_set() argument
153 etsec->regs[IEVENT].value |= flags; in ievent_set()
155 etsec_update_irq(etsec); in ievent_set()
158 static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len) in tx_padding_and_crc() argument
160 int add = min_frame_len - etsec->tx_buffer_len; in tx_padding_and_crc()
165 etsec->tx_buffer = g_realloc(etsec->tx_buffer, in tx_padding_and_crc()
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H A Detsec.c56 void etsec_update_irq(eTSEC *etsec) in etsec_update_irq() argument
58 uint32_t ievent = etsec->regs[IEVENT].value; in etsec_update_irq()
59 uint32_t imask = etsec->regs[IMASK].value; in etsec_update_irq()
72 qemu_set_irq(etsec->tx_irq, tx); in etsec_update_irq()
73 qemu_set_irq(etsec->rx_irq, rx); in etsec_update_irq()
74 qemu_set_irq(etsec->err_irq, err); in etsec_update_irq()
79 eTSEC *etsec = opaque; in etsec_read() local
86 reg = &etsec->regs[reg_index]; in etsec_read()
109 static void write_tstat(eTSEC *etsec, in write_tstat() argument
119 etsec_walk_tx_ring(etsec, i); in write_tstat()
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H A Dmiim.c32 static void miim_read_cycle(eTSEC *etsec) in miim_read_cycle() argument
38 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_read_cycle()
40 addr = etsec->regs[MIIMADD].value & 0x1F; in miim_read_cycle()
44 value = etsec->phy_control; in miim_read_cycle()
47 value = etsec->phy_status; in miim_read_cycle()
61 etsec->regs[MIIMSTAT].value = value; in miim_read_cycle()
64 static void miim_write_cycle(eTSEC *etsec) in miim_write_cycle() argument
70 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_write_cycle()
72 addr = etsec->regs[MIIMADD].value & 0x1F; in miim_write_cycle()
73 value = etsec->regs[MIIMCON].value & 0xffff; in miim_write_cycle()
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