57 void etsec_update_irq(eTSEC *etsec)  in etsec_update_irq()  argument
59     uint32_t ievent = etsec->regs[IEVENT].value;  in etsec_update_irq()
60     uint32_t imask  = etsec->regs[IMASK].value;  in etsec_update_irq()
73     qemu_set_irq(etsec->tx_irq, tx);  in etsec_update_irq()
74     qemu_set_irq(etsec->rx_irq, rx);  in etsec_update_irq()
75     qemu_set_irq(etsec->err_irq, err);  in etsec_update_irq()
80     eTSEC          *etsec     = opaque;  in etsec_read()  local
87     reg = &etsec->regs[reg_index];  in etsec_read()
110 static void write_tstat(eTSEC          *etsec,  in write_tstat()  argument
120             etsec_walk_tx_ring(etsec, i);  in write_tstat()
128 static void write_rstat(eTSEC          *etsec,  in write_rstat()  argument
138             etsec_walk_rx_ring(etsec, i);  in write_rstat()
146 static void write_tbasex(eTSEC          *etsec,  in write_tbasex()  argument
154     etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;  in write_tbasex()
157 static void write_rbasex(eTSEC          *etsec,  in write_rbasex()  argument
165     etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;  in write_rbasex()
168 static void write_dmactrl(eTSEC          *etsec,  in write_dmactrl()  argument
177         if (etsec->rx_buffer_len != 0) {  in write_dmactrl()
181             etsec->regs[IEVENT].value |= IEVENT_GRSC;  in write_dmactrl()
182             etsec_update_irq(etsec);  in write_dmactrl()
188         if (etsec->tx_buffer_len != 0) {  in write_dmactrl()
192             etsec->regs[IEVENT].value |= IEVENT_GTSC;  in write_dmactrl()
193             etsec_update_irq(etsec);  in write_dmactrl()
199         ptimer_transaction_begin(etsec->ptimer);  in write_dmactrl()
200         ptimer_stop(etsec->ptimer);  in write_dmactrl()
201         ptimer_set_count(etsec->ptimer, 1);  in write_dmactrl()
202         ptimer_run(etsec->ptimer, 1);  in write_dmactrl()
203         ptimer_transaction_commit(etsec->ptimer);  in write_dmactrl()
212     eTSEC          *etsec     = opaque;  in etsec_write()  local
219     reg = &etsec->regs[reg_index];  in etsec_write()
227         etsec_update_irq(etsec);  in etsec_write()
233         etsec_update_irq(etsec);  in etsec_write()
237         write_dmactrl(etsec, reg, reg_index, value);  in etsec_write()
241         write_tstat(etsec, reg, reg_index, value);  in etsec_write()
245         write_rstat(etsec, reg, reg_index, value);  in etsec_write()
249         write_tbasex(etsec, reg, reg_index, value);  in etsec_write()
253         write_rbasex(etsec, reg, reg_index, value);  in etsec_write()
257         etsec_write_miim(etsec, reg, reg_index, value);  in etsec_write()
298     eTSEC *etsec = opaque;  in etsec_timer_hit()  local
300     ptimer_stop(etsec->ptimer);  in etsec_timer_hit()
302     if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {  in etsec_timer_hit()
304         if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {  in etsec_timer_hit()
305             etsec_walk_tx_ring(etsec, 0);  in etsec_timer_hit()
307         ptimer_set_count(etsec->ptimer, 1);  in etsec_timer_hit()
308         ptimer_run(etsec->ptimer, 1);  in etsec_timer_hit()
314     eTSEC *etsec = ETSEC_COMMON(d);  in etsec_reset()  local
320         etsec->regs[i].name   = "Reserved";  in etsec_reset()
321         etsec->regs[i].desc   = "";  in etsec_reset()
322         etsec->regs[i].access = ACC_UNKNOWN;  in etsec_reset()
323         etsec->regs[i].value  = 0x00000000;  in etsec_reset()
331         etsec->regs[reg_index].name   = eTSEC_registers_def[i].name;  in etsec_reset()
332         etsec->regs[reg_index].desc   = eTSEC_registers_def[i].desc;  in etsec_reset()
333         etsec->regs[reg_index].access = eTSEC_registers_def[i].access;  in etsec_reset()
334         etsec->regs[reg_index].value  = eTSEC_registers_def[i].reset;  in etsec_reset()
337     etsec->tx_buffer     = NULL;  in etsec_reset()
338     etsec->tx_buffer_len = 0;  in etsec_reset()
339     etsec->rx_buffer     = NULL;  in etsec_reset()
340     etsec->rx_buffer_len = 0;  in etsec_reset()
342     etsec->phy_status =  in etsec_reset()
349     etsec_update_irq(etsec);  in etsec_reset()
357     eTSEC *etsec = qemu_get_nic_opaque(nc);  in etsec_receive()  local
364     etsec->need_flush = false;  in etsec_receive()
365     ret = etsec_rx_ring_write(etsec, buf, size);  in etsec_receive()
369         etsec->need_flush = true;  in etsec_receive()
377     eTSEC *etsec = qemu_get_nic_opaque(nc);  in etsec_set_link_status()  local
379     etsec_miim_link_status(etsec, nc);  in etsec_set_link_status()
391     eTSEC        *etsec = ETSEC_COMMON(dev);  in etsec_realize()  local
393     etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,  in etsec_realize()
395                               &dev->mem_reentrancy_guard, etsec);  in etsec_realize()
396     qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);  in etsec_realize()
398     etsec->ptimer = ptimer_init(etsec_timer_hit, etsec, PTIMER_POLICY_LEGACY);  in etsec_realize()
399     ptimer_transaction_begin(etsec->ptimer);  in etsec_realize()
400     ptimer_set_freq(etsec->ptimer, 100);  in etsec_realize()
401     ptimer_transaction_commit(etsec->ptimer);  in etsec_realize()
406     eTSEC        *etsec = ETSEC_COMMON(obj);  in etsec_instance_init()  local
409     memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,  in etsec_instance_init()
411     sysbus_init_mmio(sbd, &etsec->io_area);  in etsec_instance_init()
413     sysbus_init_irq(sbd, &etsec->tx_irq);  in etsec_instance_init()
414     sysbus_init_irq(sbd, &etsec->rx_irq);  in etsec_instance_init()
415     sysbus_init_irq(sbd, &etsec->err_irq);  in etsec_instance_init()