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Searched refs:eccpos (Results 1 – 24 of 24) sorted by relevance

/openbmc/u-boot/drivers/mtd/nand/raw/
H A Domap_gpmc.c592 uint32_t *eccpos = chip->ecc.layout->eccpos; in omap_read_page_bch() local
599 oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; in omap_read_page_bch()
600 oob += chip->ecc.layout->eccpos[0]; in omap_read_page_bch()
620 ecc_code[i] = chip->oob_poi[eccpos[i]]; in omap_read_page_bch()
751 ecclayout->eccpos[i] = i + 2; in omap_select_ecc_scheme()
753 ecclayout->eccpos[i] = i + 1; in omap_select_ecc_scheme()
786 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; in omap_select_ecc_scheme()
789 ecclayout->eccpos[i] = in omap_select_ecc_scheme()
790 ecclayout->eccpos[i - 1] + 1; in omap_select_ecc_scheme()
792 ecclayout->eccpos[i] = in omap_select_ecc_scheme()
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H A Dzynq_nand.c178 .eccpos = {0, 1, 2},
186 .eccpos = {
197 .eccpos = {
568 u32 *eccpos = chip->ecc.layout->eccpos; in zynq_nand_write_page_hwecc() local
591 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]); in zynq_nand_write_page_hwecc()
628 u32 *eccpos = chip->ecc.layout->eccpos; in zynq_nand_write_page_swecc() local
635 chip->oob_poi[eccpos[i]] = ecc_calc[i]; in zynq_nand_write_page_swecc()
661 u32 *eccpos = chip->ecc.layout->eccpos; in zynq_nand_read_page_hwecc() local
701 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]); in zynq_nand_read_page_hwecc()
734 u32 *eccpos = chip->ecc.layout->eccpos; in zynq_nand_read_page_swecc() local
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H A Ddavinci_nand.c267 .eccpos = {
277 .eccpos = {
290 .eccpos = {
310 .eccpos = {
324 .eccpos = {
427 uint32_t *eccpos; in nand_davinci_read_page_hwecc() local
439 eccpos = chip->ecc.layout->eccpos; in nand_davinci_read_page_hwecc()
447 ecc_code[i] = chip->oob_poi[eccpos[i]]; in nand_davinci_read_page_hwecc()
H A Dlpc32xx_nand_slc.c76 .eccpos = { 10, 11, 12, 13, 14, 15, },
420 uint32_t *eccpos = chip->ecc.layout->eccpos; in lpc32xx_read_page_hwecc() local
436 ecc_code[i] = chip->oob_poi[eccpos[i]]; in lpc32xx_read_page_hwecc()
458 uint32_t *eccpos = chip->ecc.layout->eccpos; in lpc32xx_write_page_hwecc() local
472 chip->oob_poi[eccpos[i]] = ecc_calc[i]; in lpc32xx_write_page_hwecc()
H A Datmel_nand.c99 layout->eccpos[i] = oobsize - ecc_len + i; in pmecc_config_ecc_layout()
470 pos = tmp + nand_chip->ecc.layout->eccpos[0]; in pmecc_correct_data()
534 uint32_t *eccpos = chip->ecc.layout->eccpos; in atmel_nand_pmecc_read_page() local
563 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0) in atmel_nand_pmecc_read_page()
574 uint32_t *eccpos = chip->ecc.layout->eccpos; in atmel_nand_pmecc_write_page() local
606 chip->oob_poi[eccpos[pos]] = in atmel_nand_pmecc_write_page()
672 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]); in atmel_pmecc_core_init()
674 ecc_layout->eccpos[ecc_layout->eccbytes - 1]); in atmel_pmecc_core_init()
964 .eccpos = {60, 61, 62, 63},
977 .eccpos = {0, 1, 2, 3},
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H A Dnand_base.c53 .eccpos = {0, 1, 2},
63 .eccpos = {0, 1, 2, 3, 6, 7},
71 .eccpos = {
82 .eccpos = {
1290 uint32_t *eccpos = chip->ecc.layout->eccpos; in nand_read_page_swecc() local
1299 ecc_code[i] = chip->oob_poi[eccpos[i]]; in nand_read_page_swecc()
1332 uint32_t *eccpos = chip->ecc.layout->eccpos; in nand_read_subpage() local
1367 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { in nand_read_subpage()
1380 aligned_pos = eccpos[index] & ~(busw - 1); in nand_read_subpage()
1382 if (eccpos[index] & (busw - 1)) in nand_read_subpage()
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H A Dfsmc_nand.c31 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
67 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
120 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
137 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
H A Dfsl_ifc_nand.c64 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
71 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
78 .eccpos = {
90 .eccpos = {
106 .eccpos = {
130 .eccpos = {
154 .eccpos = {
H A Dfsl_elbc_nand.c81 .eccpos = {6, 7, 8},
88 .eccpos = {8, 9, 10},
95 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
102 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
H A Dpxa3xx_nand.c319 .eccpos = {
329 .eccpos = {
343 .eccpos = {
358 .eccpos = {
385 .eccpos = {
395 .eccpos = {},
H A Dnand_bch.c173 layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; in nand_bch_init()
H A Dmxc_nand.c53 .eccpos = {6, 7, 8, 9, 10},
59 .eccpos = {
72 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
78 .eccpos = {
H A Dvf610_nfc.c168 .eccpos = {19, 20, 21, 22, 23,
183 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
H A Dlpc32xx_nand_mlc.c202 .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
H A Darasan_nfc.c215 .eccpos = {
1174 nand_oob.eccpos[i] = eccpos_start + i; in arasan_nand_ecc_init()
H A Dsunxi_nand.c1498 layout->eccpos[(ecc->bytes * i) + j] = in sunxi_nand_hw_ecc_ctrl_init()
1535 layout->eccpos[i] = i; in sunxi_nand_hw_syndrome_ecc_ctrl_init()
H A Dtegra_nand.c51 .eccpos = {
/openbmc/linux/drivers/mtd/
H A Dmtdchar.c456 u32 eccpos; in shrink_ecclayout() local
466 eccpos = oobregion.offset; in shrink_ecclayout()
468 eccpos < oobregion.offset + oobregion.length; i++) { in shrink_ecclayout()
469 to->eccpos[i] = eccpos++; in shrink_ecclayout()
502 for (i = 0; i < ARRAY_SIZE(to->eccpos);) { in get_oobinfo()
503 u32 eccpos; in get_oobinfo() local
513 if (oobregion.length + i > ARRAY_SIZE(to->eccpos)) in get_oobinfo()
516 eccpos = oobregion.offset; in get_oobinfo()
517 for (; eccpos < oobregion.offset + oobregion.length; i++) { in get_oobinfo()
518 to->eccpos[i] = eccpos++; in get_oobinfo()
/openbmc/u-boot/include/mtd/
H A Dmtd-abi.h205 __u32 eccpos[32]; member
225 __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES]; member
/openbmc/linux/include/uapi/mtd/
H A Dmtd-abi.h272 __u32 eccpos[32]; member
292 __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES]; member
/openbmc/u-boot/doc/
H A DREADME.omap3159 * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
/openbmc/u-boot/include/linux/mtd/
H A Dmtd.h144 __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; member
/openbmc/u-boot/drivers/mtd/onenand/
H A Donenand_base.c52 .eccpos = {
72 .eccpos = {
89 .eccpos = {
/openbmc/linux/Documentation/driver-api/
H A Dmtdnand.rst625 int eccpos[24];
643 - eccpos
645 The eccpos array holds the byte offsets in the spare area where the