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/openbmc/openbmc/poky/meta/conf/machine/include/powerpc/
H A Dtune-ppce6500.inc5 TUNEVALID[e6500] = "Enable Freescale e6500 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'e6500', ' -mcpu=e6500', '', d)}"
9 TUNE_FEATURES:tune-ppce6500 = "m32 fpu-hard e6500 altivec bigendian"
15 TUNE_FEATURES:tune-ppc64e6500 = "m64 fpu-hard e6500 altivec bigendian"
22 MACHINE_FEATURES_BACKFILL_CONSIDERED:append = "${@bb.utils.contains('TUNE_FEATURES', 'e6500', ' qem…
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-pre.dtsi90 cpu0: PowerPC,e6500@0 {
97 cpu1: PowerPC,e6500@2 {
104 cpu2: PowerPC,e6500@4 {
111 cpu3: PowerPC,e6500@6 {
118 cpu4: PowerPC,e6500@8 {
125 cpu5: PowerPC,e6500@10 {
132 cpu6: PowerPC,e6500@12 {
139 cpu7: PowerPC,e6500@14 {
146 cpu8: PowerPC,e6500@16 {
153 cpu9: PowerPC,e6500@18 {
[all …]
H A Dt208xsi-pre.dtsi81 cpu0: PowerPC,e6500@0 {
88 cpu1: PowerPC,e6500@2 {
95 cpu2: PowerPC,e6500@4 {
102 cpu3: PowerPC,e6500@6 {
H A Db4860si-pre.dtsi75 cpu0: PowerPC,e6500@0 {
82 cpu1: PowerPC,e6500@2 {
89 cpu2: PowerPC,e6500@4 {
96 cpu3: PowerPC,e6500@6 {
H A Dt4240si-post.dtsi251 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
256 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
261 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
266 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
271 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
276 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
281 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
286 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
291 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
296 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
[all …]
H A Db4420si-pre.dtsi70 cpu0: PowerPC,e6500@0 {
77 cpu1: PowerPC,e6500@2 {
H A Db4860si-post.dtsi94 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
99 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
104 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
H A Dt2081si-post.dtsi221 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
226 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
231 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
236 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
H A De6500_power_isa.dtsi2 * e6500 Power ISA Device Tree Source (include)
H A Db4420si-post.dtsi68 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
H A Db4si-post.dtsi140 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
/openbmc/u-boot/arch/powerpc/dts/
H A Dt2080.dtsi22 cpu0: PowerPC,e6500@0 {
27 cpu1: PowerPC,e6500@2 {
32 cpu2: PowerPC,e6500@4 {
37 cpu3: PowerPC,e6500@6 {
H A De6500_power_isa.dtsi3 * e6500 Power ISA Device Tree Source (include)
/openbmc/linux/Documentation/powerpc/
H A Disa-versions.rst15 e6500 Power ISA v2.06 with some exceptions
49 e6500 Yes
69 e6500 No
89 e6500 No
H A Dcpu_families.rst186 - e6500 adds HW loaded indirect TLB entries.
219 | e6500 (HW TLB) (Multithreaded) |
/openbmc/qemu/docs/system/ppc/
H A Dppce500.rst12 * PowerPC e500 series core (e500v2/e500mc/e5500/e6500)
49 * e6500
52 it creates a machine with e500v2 core. The following example shows an e6500
57 $ qemu-system-ppc64 -nographic -M ppce500 -cpu e6500
137 When U-Boot boots, you will notice the following if using with ``-cpu e6500``:
142 Core: e6500, Version: 2.0, (0x80400020)
148 built for P4080 (e500mc), P5020 (e5500) and T2080 (e6500).
/openbmc/u-boot/doc/
H A DREADME.b4860qds18 . Four dual-thread e6500 Power Architecture processors organized in one cluster-each
28 e6500 cores, SC3900 FVP cores, memories and external interfaces.
45 . 32 Kbyte L1 ICache per e6500/SC3900 core
46 . 32 Kbyte L1 DCache per e6500/SC3900 core
48 . 2048 Kbyte unified L2 cache for the e6500 cluster
101 B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR
108 1. Less e6500 cores: 1 cluster with 2 e6500 cores
130 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
155 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
H A DREADME.Heterogeneous-SoCs89 Core: e6500, Version: 2.0, (0x80400020) Clock Configuration:
/openbmc/linux/arch/powerpc/perf/
H A DMakefile15 obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
52 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
/openbmc/linux/arch/powerpc/platforms/
H A DKconfig.cputype192 bool "Freescale e6500"
264 default "e6500" if E6500_CPU
305 such as e5500/e6500), and must be disabled for running on
/openbmc/qemu/target/ppc/
H A Dcpu-models.c310 CPU_POWERPC_e6500, POWERPC_SVR_E500, e6500)
H A Dcpu_init.c3215 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) in POWERPC_FAMILY()
3220 dc->desc = "e6500 core"; in init_proc_e6500()
3223 POWERPC_FAMILY(e6500) POWERPC_FAMILY() argument