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Searched refs:dxcc_parents (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c211 static const char * const dxcc_parents[] = { variable
564 dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23),
H A Dclk-mt8183.c405 static const char * const dxcc_parents[] = { variable
541 dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
H A Dclk-mt8365.c251 static const char * const dxcc_parents[] = { variable
475 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
H A Dclk-mt8192.c382 static const char * const dxcc_parents[] = { variable
647 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
H A Dclk-mt8195-topckgen.c470 static const char * const dxcc_parents[] = { variable
1004 dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
H A Dclk-mt6779.c504 static const char * const dxcc_parents[] = { variable
741 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
H A Dclk-mt6765.c300 static const char * const dxcc_parents[] = { variable
438 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,