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Searched refs:dwc3_reg (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/usb/host/
H A Dxhci-dwc3.c27 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) in dwc3_set_mode() argument
29 clrsetbits_le32(&dwc3_reg->g_ctl, in dwc3_set_mode()
34 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) in dwc3_phy_reset() argument
37 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); in dwc3_phy_reset()
40 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); in dwc3_phy_reset()
45 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); in dwc3_phy_reset()
48 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); in dwc3_phy_reset()
51 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) in dwc3_core_soft_reset() argument
54 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); in dwc3_core_soft_reset()
57 dwc3_phy_reset(dwc3_reg); in dwc3_core_soft_reset()
[all …]
H A Dxhci-fsl.c59 static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg) in fsl_xhci_set_beat_burst_length() argument
61 clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK, in fsl_xhci_set_beat_burst_length()
63 setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT); in fsl_xhci_set_beat_burst_length()
70 ret = dwc3_core_init(fsl_xhci->dwc3_reg); in fsl_xhci_core_init()
77 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); in fsl_xhci_core_init()
80 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT); in fsl_xhci_core_init()
83 fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg); in fsl_xhci_core_init()
94 clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0], in fsl_xhci_core_init()
128 priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) + in xhci_fsl_probe()
182 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); in xhci_hcd_init()
H A Dxhci-rockchip.c31 struct dwc3 *dwc3_reg; member
62 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, in rockchip_dwc3_phy_setup() argument
69 reg = readl(&dwc3_reg->g_usb2phycfg[0]); in rockchip_dwc3_phy_setup()
91 writel(reg, &dwc3_reg->g_usb2phycfg[0]); in rockchip_dwc3_phy_setup()
99 ret = dwc3_core_init(rkxhci->dwc3_reg); in rockchip_xhci_core_init()
105 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); in rockchip_xhci_core_init()
108 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); in rockchip_xhci_core_init()
126 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); in xhci_usb_probe()
H A Dxhci-zynqmp.c61 struct dwc3 *dwc3_reg; member
72 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); in zynqmp_xhci_core_init()
79 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); in zynqmp_xhci_core_init()
102 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); in xhci_usb_probe()
H A Dxhci-omap.c34 ret = dwc3_core_init(omap->dwc3_reg); in omap_xhci_core_init()
41 dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); in omap_xhci_core_init()
57 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); in xhci_hcd_init()
H A Dxhci-exynos5.c50 struct dwc3 *dwc3_reg; member
187 ret = dwc3_core_init(exynos->dwc3_reg); in exynos_xhci_core_init()
194 dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); in exynos_xhci_core_init()
213 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); in xhci_usb_probe()
/openbmc/u-boot/include/linux/usb/
H A Ddwc3.h218 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
219 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
220 int dwc3_core_init(struct dwc3 *dwc3_reg);
221 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
H A Dxhci-omap.h137 struct dwc3 *dwc3_reg; member
142 void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
H A Dxhci-fsl.h53 struct dwc3 *dwc3_reg; member