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Searched refs:dram_info (Results 1 – 25 of 27) sorted by relevance

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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c46 MV_DRAM_INFO *dram_info);
50 MV_DRAM_INFO *dram_info);
61 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_hw() argument
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
93 dram_info->rl_max_phase = 0; in ddr3_read_leveling_hw()
94 dram_info->rl_min_phase = 10; in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
100 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
102 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
103 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
[all …]
H A Dddr3_hw_training.c84 MV_DRAM_INFO dram_info; in ddr3_hw_training() local
92 memset(&dram_info, 0, sizeof(dram_info)); in ddr3_hw_training()
93 dram_info.num_cs = ddr3_get_cs_num_from_reg(); in ddr3_hw_training()
94 dram_info.cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_hw_training()
95 dram_info.target_frequency = target_freq; in ddr3_hw_training()
96 dram_info.ddr_width = ddr_width; in ddr3_hw_training()
97 dram_info.num_of_std_pups = ddr_width / PUP_SIZE; in ddr3_hw_training()
98 dram_info.rl400_bug = 0; in ddr3_hw_training()
99 dram_info.multi_cs_mr_support = 0; in ddr3_hw_training()
101 dram_info.rl400_bug = 1; in ddr3_hw_training()
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H A Dddr3_write_leveling.c48 MV_DRAM_INFO *dram_info);
64 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_hw() argument
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
109 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
111 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
112 && dram_info->ecc_ena) in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
[all …]
H A Dddr3_hw_training.h251 typedef struct dram_info { struct
329 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
334 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
339 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
344 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
349 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
353 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
355 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
356 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
358 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
[all …]
H A Dddr3_dqs.c67 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx);
70 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
72 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
74 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
76 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
92 static u32 *ddr3_dqs_choose_pattern(MV_DRAM_INFO *dram_info, u32 victim_dq) in ddr3_dqs_choose_pattern() argument
97 switch (dram_info->ddr_width) { in ddr3_dqs_choose_pattern()
130 int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info) in ddr3_dqs_centralization_rx() argument
151 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
155 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_dqs_centralization_rx()
[all …]
H A Dddr3_pbs.c59 static int ddr3_tx_shift_dqs_adll_step_before_fail(MV_DRAM_INFO *dram_info,
61 static int ddr3_rx_shift_dqs_to_first_fail(MV_DRAM_INFO *dram_info, u32 cur_pup,
63 static int ddr3_pbs_per_bit(MV_DRAM_INFO *dram_info, int *start_over, int is_tx,
65 static int ddr3_set_pbs_results(MV_DRAM_INFO *dram_info, int is_tx);
75 int ddr3_pbs_tx(MV_DRAM_INFO *dram_info) in ddr3_pbs_tx() argument
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
135 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_tx()
142 dram_info->num_of_std_pups + ecc; in ddr3_pbs_tx()
161 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_tx()
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H A Dddr3_dfs.c112 int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_dfs_high_2_low() argument
153 if (dram_info->reg_dimm) { in ddr3_dfs_high_2_low()
196 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
393 if (dram_info->reg_dimm) { in ddr3_dfs_high_2_low()
442 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
468 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
676 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
768 int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_dfs_low_2_high() argument
971 reg |= ((dram_info->mode_2t & REG_DUNIT_CTRL_LOW_2T_MASK) << in ddr3_dfs_low_2_high()
982 if (dram_info->target_frequency == 0x8) in ddr3_dfs_low_2_high()
[all …]
H A Dddr3_sdram.c163 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_compare() argument
174 if (dram_info->num_of_std_pups == PUP_NUM_64BIT) in ddr3_sdram_compare()
219 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_dm_compare() argument
227 if (dram_info->num_of_std_pups == PUP_NUM_64BIT) in ddr3_sdram_dm_compare()
280 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, in ddr3_sdram_pbs_compare() argument
298 switch (dram_info->ddr_width) { in ddr3_sdram_pbs_compare()
316 max_pup = dram_info->num_of_std_pups; in ddr3_sdram_pbs_compare()
320 if (dram_info->num_of_std_pups == PUP_NUM_64BIT) in ddr3_sdram_pbs_compare()
348 if (dram_info->ddr_width > 16) { in ddr3_sdram_pbs_compare()
441 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_direct_compare() argument
[all …]
H A Dxor.c23 void mv_sys_xor_init(MV_DRAM_INFO *dram_info) in mv_sys_xor_init() argument
34 for (ui = 0; ui < (dram_info->num_cs + 1); ui++) { in mv_sys_xor_init()
45 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
47 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
51 if (dram_info->cs_ena & (1 << ui)) { in mv_sys_xor_init()
H A Dxor.h64 void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c337 struct dram_info *dram_info = &i915->dram_info; in skl_dram_get_channels_info() local
346 dram_info->num_channels++; in skl_dram_get_channels_info()
352 dram_info->num_channels++; in skl_dram_get_channels_info()
354 if (dram_info->num_channels == 0) { in skl_dram_get_channels_info()
364 dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm; in skl_dram_get_channels_info()
366 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); in skl_dram_get_channels_info()
369 str_yes_no(dram_info->symmetric_memory)); in skl_dram_get_channels_info()
400 struct dram_info *dram_info = &i915->dram_info; in skl_get_dram_info() local
403 dram_info->type = skl_get_dram_type(i915); in skl_get_dram_info()
405 intel_dram_type_str(dram_info->type)); in skl_get_dram_info()
[all …]
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c82 struct dram_info { struct
109 static void ast2500_ddr_phy_init_process(struct dram_info *info) in ast2500_ddr_phy_init_process() argument
123 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref) in ast2500_sdrammc_set_vref()
130 static int ast2500_ddr_cbr_test(struct dram_info *info) in ast2500_ddr_cbr_test()
170 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) in ast2500_sdrammc_ddr4_calibrate_vref()
198 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) in ast2500_sdrammc_get_vga_mem_size()
207 static void ast2500_sdrammc_update_size(struct dram_info *info) in ast2500_sdrammc_update_size()
237 static void ast2500_sdrammc_calc_size(struct dram_info *info) in ast2500_sdrammc_calc_size()
281 static void ast2500_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb) in ast2500_sdrammc_ecc_enable()
318 struct dram_info *info = dev_get_priv(dev); in ast2500_sdrammc_init_ddr4()
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H A Dsdram_ast2600.c195 struct dram_info { struct
206 static void ast2600_sdramphy_kick_training(struct dram_info *info) in ast2600_sdramphy_kick_training() argument
235 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) in ast2600_sdramphy_init()
271 static int ast2600_sdramphy_check_status(struct dram_info *info) in ast2600_sdramphy_check_status()
373 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) in ast2600_sdrammc_dg_test()
404 int ast2600_sdrammc_cbr_test(struct dram_info *info) in ast2600_sdrammc_cbr_test()
426 static int ast2600_sdrammc_test(struct dram_info *info) in ast2600_sdrammc_test()
475 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) in ast2600_sdrammc_get_vga_mem_size()
501 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) in ast2600_sdrammc_fpga_set_pll()
515 static int ast2600_sdrammc_search_read_window(struct dram_info *info) in ast2600_sdrammc_search_read_window()
[all …]
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3328.c14 struct dram_info { struct
21 struct dram_info *priv = dev_get_priv(dev); in rk3328_dmc_probe() argument
34 struct dram_info *priv = dev_get_priv(dev); in rk3328_dmc_get_info()
57 .priv_auto_alloc_size = sizeof(struct dram_info),
H A Dsdram_rk3128.c14 struct dram_info { struct
21 struct dram_info *priv = dev_get_priv(dev); in rk3128_dmc_probe() argument
34 struct dram_info *priv = dev_get_priv(dev); in rk3128_dmc_get_info()
56 .priv_auto_alloc_size = sizeof(struct dram_info),
H A Dsdram_rk322x.c32 struct dram_info { struct
363 static void phy_softreset(struct dram_info *dram) in phy_softreset()
378 static void set_bw(struct dram_info *dram, u32 bw) in set_bw()
577 static void dram_all_config(const struct dram_info *dram, in dram_all_config()
600 static int dram_cap_detect(struct dram_info *dram, in dram_cap_detect()
685 static int sdram_init(struct dram_info *dram, in sdram_init()
786 struct dram_info *priv = dev_get_priv(dev); in rk322x_dmc_probe()
824 struct dram_info *priv = dev_get_priv(dev); in rk322x_dmc_get_info()
849 .priv_auto_alloc_size = sizeof(struct dram_info),
H A Dsdram_rk3288.c35 struct dram_info { struct
589 static void dram_all_config(const struct dram_info *dram, in dram_all_config()
617 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect()
670 static int sdram_col_row_detect(struct dram_info *dram, int channel, in sdram_col_row_detect()
780 static int sdram_init(struct dram_info *dram, in sdram_init()
926 static int veyron_init(struct dram_info *priv) in veyron_init()
953 struct dram_info *priv = dev_get_priv(dev); in setup_sdram()
999 struct dram_info *priv = dev_get_priv(dev); in rk3288_dmc_ofdata_to_platdata()
1044 struct dram_info *priv = dev_get_priv(dev); in rk3288_dmc_probe()
1093 struct dram_info *priv = dev_get_priv(dev); in rk3288_dmc_get_info()
[all …]
H A Dsdram_rk3188.c33 struct dram_info { struct
532 static void dram_all_config(const struct dram_info *dram, in dram_all_config()
564 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect()
625 static int sdram_col_row_detect(struct dram_info *dram, int channel, in sdram_col_row_detect()
709 static int sdram_init(struct dram_info *dram, in sdram_init()
807 struct dram_info *priv = dev_get_priv(dev); in setup_sdram()
883 struct dram_info *priv = dev_get_priv(dev); in rk3188_dmc_probe()
928 struct dram_info *priv = dev_get_priv(dev); in rk3188_dmc_get_info()
953 .priv_auto_alloc_size = sizeof(struct dram_info),
H A Ddmc-rk3368.c22 struct dram_info { struct
601 struct dram_info *priv = dev_get_priv(dev); in sdram_col_row_detect()
770 struct dram_info *priv = dev_get_priv(dev); in dram_all_config()
795 struct dram_info *priv = dev_get_priv(dev); in setup_sdram()
914 struct dram_info *priv = dev_get_priv(dev); in rk3368_dmc_probe()
970 struct dram_info *priv = dev_get_priv(dev); in rk3368_dmc_get_info()
992 .priv_auto_alloc_size = sizeof(struct dram_info),
995 .priv_auto_alloc_size = sizeof(struct dram_info),
H A Dsdram_rk3399.c32 struct dram_info { struct
931 static void dram_all_config(struct dram_info *dram, in dram_all_config()
991 static int switch_to_phy_index1(struct dram_info *dram, in switch_to_phy_index1()
1037 static int sdram_init(struct dram_info *dram, in sdram_init()
1128 struct dram_info *priv = dev_get_priv(dev); in rk3399_dmc_init()
1194 struct dram_info *priv = dev_get_priv(dev); in rk3399_dmc_probe()
1207 struct dram_info *priv = dev_get_priv(dev); in rk3399_dmc_get_info()
1233 .priv_auto_alloc_size = sizeof(struct dram_info),
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c214 const struct dram_info *dram_info = &dev_priv->dram_info; in icl_get_qgv_points() local
217 qi->num_points = dram_info->num_qgv_points; in icl_get_qgv_points()
218 qi->num_psf_points = dram_info->num_psf_gv_points; in icl_get_qgv_points()
221 switch (dram_info->type) { in icl_get_qgv_points()
242 MISSING_CASE(dram_info->type); in icl_get_qgv_points()
246 switch (dram_info->type) { in icl_get_qgv_points()
280 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; in icl_get_qgv_points()
389 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in icl_get_bw_info()
457 const struct dram_info *dram_info = &dev_priv->dram_info; in tgl_get_bw_info() local
459 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in tgl_get_bw_info()
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-dbg-tlv.c744 struct iwl_dram_info *dram_info) in iwl_dbg_tlv_update_dram() argument
771 data = &dram_info->dram_frags[alloc_id - 1]; in iwl_dbg_tlv_update_dram()
799 struct iwl_dram_info *dram_info; in iwl_dbg_tlv_update_drams() local
804 dram_info = frags->block; in iwl_dbg_tlv_update_drams()
810 memset(dram_info, 0, sizeof(*dram_info)); in iwl_dbg_tlv_update_drams()
818 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); in iwl_dbg_tlv_update_drams()
828 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); in iwl_dbg_tlv_update_drams()
829 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); in iwl_dbg_tlv_update_drams()
901 struct iwl_dbgc1_info dram_info = {}; in iwl_dbg_tlv_apply_config() local
921 dram_info.dbgc1_add_lsb = in iwl_dbg_tlv_apply_config()
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dtx.h273 struct iwl_dram_sec_info dram_info; member
295 struct iwl_dram_sec_info dram_info; member
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_drv.h297 struct dram_info { struct
312 } dram_info; member
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/queue/
H A Dtx.c661 offsetofend(struct iwl_tx_cmd_gen2, dram_info) > in iwl_txq_gen2_build_tfd()
665 offsetofend(struct iwl_tx_cmd_gen3, dram_info) > in iwl_txq_gen2_build_tfd()

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