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Searched refs:dram (Results 1 – 25 of 87) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c60 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
100 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_set_drive() local
103 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
105 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
113 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_itm_disable() local
115 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
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H A DKconfig12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
398 int "sunxi dram type"
402 Set the dram type, 3: DDR3, 7: LPDDR3
405 int "sunxi dram clock speed"
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c24 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
36 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
37 writel(dram->config0, &emc->config0); in ddr_init()
38 writel(dram->rascas0, &emc->rascas0); in ddr_init()
39 writel(dram->rdconfig, &emc->read_config); in ddr_init()
41 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
43 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
44 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
45 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); in ddr_init()
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H A DMakefile8 obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk322x.c363 static void phy_softreset(struct dram_info *dram) in phy_softreset() argument
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
366 struct rk322x_grf *grf = dram->grf; in phy_softreset()
378 static void set_bw(struct dram_info *dram, u32 bw) in set_bw() argument
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw()
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
382 struct rk322x_grf *grf = dram->grf; in set_bw()
577 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
595 writel(sys_reg, &dram->grf->os_reg[2]); in dram_all_config()
600 static int dram_cap_detect(struct dram_info *dram, in dram_cap_detect() argument
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H A Dsdram_rk3188.c532 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
554 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
557 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
559 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
561 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
564 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
569 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
572 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
595 dram->grf); in sdram_rank_bw_detect()
605 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
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H A Dsdram_rk3288.c589 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
611 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
613 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
614 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
617 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
622 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
648 dram->grf); in sdram_rank_bw_detect()
658 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
660 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
670 static int sdram_col_row_detect(struct dram_info *dram, int channel, in sdram_col_row_detect() argument
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H A Dsdram_rk3399.c931 static void dram_all_config(struct dram_info *dram, in dram_all_config() argument
961 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
976 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
980 writel(sys_reg, &dram->pmugrf->os_reg2); in dram_all_config()
981 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, in dram_all_config()
987 &dram->pmucru->pmucru_rstnhold_con[1]); in dram_all_config()
988 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); in dram_all_config()
991 static int switch_to_phy_index1(struct dram_info *dram, in switch_to_phy_index1() argument
1002 &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1003 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { in switch_to_phy_index1()
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/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A DMakefile5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
/openbmc/u-boot/arch/x86/dts/
H A Dgalileo.dts51 dram-width = <DRAM_WIDTH_X8>;
52 dram-speed = <DRAM_FREQ_800>;
53 dram-type = <DRAM_TYPE_DDR3>;
63 dram-density = <DRAM_DENSITY_1G>;
64 dram-cl = <6>;
65 dram-ras = <0x0000927c>;
66 dram-wtr = <0x00002710>;
67 dram-rrd = <0x00002710>;
68 dram-faw = <0x00009c40>;
/openbmc/u-boot/arch/arm/mach-mvebu/
H A Dcpu.c514 const struct mbus_dram_target_info *dram; in ahci_mvebu_mbus_config() local
517 dram = mvebu_mbus_dram_info(); in ahci_mvebu_mbus_config()
525 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
526 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
529 (dram->mbus_dram_target_id << 4) | 1, in ahci_mvebu_mbus_config()
563 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
572 for (i = 0; i < dram->num_cs; i++) { in xhci_mvebu_mbus_config()
573 const struct mbus_dram_window *cs = dram->cs + i; in xhci_mvebu_mbus_config()
577 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
587 const struct mbus_dram_target_info *dram; in board_xhci_enable() local
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H A DMakefile15 obj-y = dram.o
22 obj-y += dram.o
/openbmc/u-boot/drivers/mmc/
H A Dmv_sdhci.c16 const struct mbus_dram_target_info *dram; in sdhci_mvebu_mbus_config() local
19 dram = mvebu_mbus_dram_info(); in sdhci_mvebu_mbus_config()
26 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
27 const struct mbus_dram_window *cs = dram->cs + i; in sdhci_mvebu_mbus_config()
31 (dram->mbus_dram_target_id << 4) | 1, in sdhci_mvebu_mbus_config()
/openbmc/u-boot/drivers/ata/
H A Dmvsata_ide.c107 const struct mbus_dram_target_info *dram; in mvsata_ide_conf_mbus_windows() local
110 dram = mvebu_mbus_dram_info(); in mvsata_ide_conf_mbus_windows()
118 for (i = 0; i < dram->num_cs; i++) { in mvsata_ide_conf_mbus_windows()
119 const struct mbus_dram_window *cs = dram->cs + i; in mvsata_ide_conf_mbus_windows()
121 (dram->mbus_dram_target_id << 4) | 1, in mvsata_ide_conf_mbus_windows()
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A DKconfig2 bool "imx8m dram"
17 hex "Define the base address for saved dram timing"
19 after DRAM is trained, need to save the dram related timming
/openbmc/u-boot/drivers/usb/host/
H A Dehci-marvell.c55 const struct mbus_dram_target_info *dram; in usb_brg_adrdec_setup() local
58 dram = mvebu_mbus_dram_info(); in usb_brg_adrdec_setup()
65 for (i = 0; i < dram->num_cs; i++) { in usb_brg_adrdec_setup()
66 const struct mbus_dram_window *cs = dram->cs + i; in usb_brg_adrdec_setup()
70 (dram->mbus_dram_target_id << 4) | 1, in usb_brg_adrdec_setup()
/openbmc/u-boot/drivers/video/
H A Dmvebu_lcd.c100 const struct mbus_dram_target_info *dram; in mvebu_lcd_conf_mbus_registers() local
103 dram = mvebu_mbus_dram_info(); in mvebu_lcd_conf_mbus_registers()
113 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
114 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
116 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dboard_common.c188 u32 dram = ast_sdmc_get_mem_size(); in dram_init()
198 gd->ram_size = dram - vga; in dram_init()
204 gd->ram_size = dram - vga; in dram_init()
/openbmc/u-boot/arch/mips/mach-bmips/
H A DMakefile3 obj-y += dram.o
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dboard_common.c144 u32 dram = ast_sdmc_get_mem_size(); in dram_init() local
145 gd->ram_size = (dram - vga); in dram_init()
/openbmc/u-boot/arch/riscv/cpu/generic/
H A DMakefile5 obj-y += dram.o
/openbmc/u-boot/arch/arm/cpu/arm926ejs/armada100/
H A DMakefile7 obj-y = cpu.o timer.o dram.o
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dsys_proto.h20 void ddr_init(const struct emc_dram_settings *dram);
/openbmc/u-boot/arch/mips/mach-ath79/
H A DMakefile5 obj-y += dram.o
/openbmc/u-boot/arch/x86/cpu/qemu/
H A DMakefile8 obj-y += dram.o

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