| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-sun9i-cpus.c | 72 static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp, in sun9i_a80_cpus_clk_round() argument
105 if (divp) { in sun9i_a80_cpus_clk_round()
106 *divp = div - 1; in sun9i_a80_cpus_clk_round()
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 62 u32 divp, u32 cpcon, u32 lfcon);
89 u32 *divp, u32 *cpcon, u32 *lfcon);
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| H A D | warmboot.h | 75 u32 divp:3; member
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot.c | 153 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
155 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
160 scratch2.pllm_base_divp = divp; in warmboot_save_sdram_params()
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| H A D | warmboot_avp.c | 172 pllx_base.divp = scratch3.pllx_base_divp; in wb_start()
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | clock.c | 90 u32 *divp, u32 *cpcon, u32 *lfcon) in clock_ll_read_pll() argument
104 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; in clock_ll_read_pll()
114 u32 divp, u32 cpcon, u32 lfcon) in clock_start_pll() argument
148 data |= divp << pllinfo->p_shift; in clock_start_pll()
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| H A D | cpu.c | 171 u32 divp, u32 cpcon) in pllx_set_rate() argument
188 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | si2165.c | 205 u8 divp = 1; /* only 1 or 4 */ in si2165_init_pll() local
221 divp = 4; in si2165_init_pll()
234 divp = 4; in si2165_init_pll()
237 divn = 1624000000u * divr / (ref_freq_hz * 2u * divp); in si2165_init_pll()
243 * 2u * divn * divp; in si2165_init_pll()
250 buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80; in si2165_init_pll()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32h7.c | 322 u8 divp; member
335 .divp = 2,
399 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; in configure_clocks()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 1066 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1074 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) in clock_set_display_rate()
1083 best_p = divp; in clock_set_display_rate()
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| /openbmc/linux/drivers/gpu/drm/tegra/ |
| H A D | dsi.c | 390 unsigned int *mulp, unsigned int *divp) in tegra_dsi_get_muldiv() argument
396 *divp = 1; in tegra_dsi_get_muldiv()
401 *divp = 1; in tegra_dsi_get_muldiv()
406 *divp = 4; in tegra_dsi_get_muldiv()
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-pll.c | 1021 u32 divn = 0, divm = 0, divp = 0; in clk_plle_recalc_rate() local
1024 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1027 divm *= divp; in clk_plle_recalc_rate()
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| /openbmc/linux/drivers/scsi/sym53c8xx_2/ |
| H A D | sym_hipd.c | 469 sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) argument
516 *divp = div;
554 *divp = div;
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