Home
last modified time | relevance | path

Searched refs:div_clks (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.c149 .div_clks = aud_div_clks,
339 .div_clks = disp_div_clks,
405 .div_clks = egl_div_clks,
594 .div_clks = g2d_div_clks,
657 .div_clks = g3d_div_clks,
790 .div_clks = gscl_div_clks,
909 .div_clks = isp_div_clks,
975 .div_clks = kfc_div_clks,
1029 .div_clks = mfc_div_clks,
1178 .div_clks = mif_div_clks,
[all …]
H A Dclk-exynos850.c497 .div_clks = top_div_clks,
635 .div_clks = apm_div_clks,
918 .div_clks = aud_div_clks,
1021 .div_clks = cmgp_div_clks,
1119 .div_clks = g3d_div_clks,
1353 .div_clks = is_div_clks,
1462 .div_clks = mfcmscl_div_clks,
1638 .div_clks = peri_div_clks,
1745 .div_clks = core_div_clks,
1819 .div_clks = dpu_div_clks,
H A Dclk-exynos5-subcmu.h14 const struct samsung_div_clock *div_clks; member
H A Dclk-exynos3250.c331 static const struct samsung_div_clock div_clks[] __initconst = { variable
807 .div_clks = div_clks,
808 .nr_div_clks = ARRAY_SIZE(div_clks),
929 .div_clks = dmc_div_clks,
1071 .div_clks = isp_div_clks,
H A Dclk-exynos7.c191 .div_clks = topc_div_clks,
383 .div_clks = top0_div_clks,
565 .div_clks = top1_div_clks,
1099 .div_clks = fsys1_div_clks,
1212 .div_clks = mscl_div_clks,
1301 .div_clks = aud_div_clks,
H A Dclk-fsd.c299 .div_clks = cmu_div_clks,
662 .div_clks = peric_div_clks,
961 .div_clks = fsys0_div_clks,
1133 .div_clks = fsys1_div_clks,
1412 .div_clks = imem_div_clks,
1537 .div_clks = mfc_div_clks,
1741 .div_clks = cam_csi_div_clks,
H A Dclk-exynosautov9.c949 .div_clks = top_div_clks,
1011 .div_clks = busmc_div_clks,
1069 .div_clks = core_div_clks,
1436 .div_clks = fsys1_div_clks,
1758 .div_clks = peric0_div_clks,
2013 .div_clks = peric1_div_clks,
H A Dclk.c350 if (cmu->div_clks) in samsung_cmu_register_clocks()
351 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks); in samsung_cmu_register_clocks()
H A Dclk-s5pv210.c477 static const struct samsung_div_clock div_clks[] __initconst = { variable
777 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); in __s5pv210_clk_init()
H A Dclk-exynos5433.c816 .div_clks = top_div_clks,
899 .div_clks = cpif_div_clks,
1551 .div_clks = mif_div_clks,
1752 .div_clks = peric_div_clks,
2481 .div_clks = g2d_div_clks,
2905 .div_clks = disp_div_clks,
3077 .div_clks = aud_div_clks,
3211 .div_clks = bus##id##_div_clks, \
3362 .div_clks = g3d_div_clks,
3713 .div_clks = apollo_div_clks,
[all …]
H A Dclk-exynos5-subcmu.c109 samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks); in exynos5_subcmu_probe()
H A Dclk-exynos7885.c338 .div_clks = top_div_clks,
666 .div_clks = core_div_clks,
H A Dclk-exynos5420.c1330 .div_clks = exynos5x_disp_div_clks,
1340 .div_clks = exynos5x_gsc_div_clks,
1358 .div_clks = exynos5x_mfc_div_clks,
1368 .div_clks = exynos5x_mscl_div_clks,
H A Dclk-exynos5410.c262 .div_clks = exynos5410_div_clks,
H A Dclk.h313 const struct samsung_div_clock *div_clks; member
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c823 static struct tegra_periph_init_data div_clks[] = { variable
919 for (i = 0; i < ARRAY_SIZE(div_clks); i++) { in div_clk_init()
922 data = div_clks + i; in div_clk_init()