| /openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
| H A D | clk.c | 34 u32 val, ctrl, xtal, pll, div; in get_clocks() local
44 div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
46 pll = xtal / div; in get_clocks()
49 div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
51 pll *= div; in get_clocks()
52 div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) in get_clocks()
54 if (!div) in get_clocks()
55 div = 1; in get_clocks()
56 pll >>= div; in get_clocks()
59 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
[all …]
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| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | clk.c | 34 u32 val, xtal, pll, div; in get_clocks() local
42 div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
44 pll = xtal / div; in get_clocks()
47 div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
49 pll *= div; in get_clocks()
50 div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) in get_clocks()
52 if (!div) in get_clocks()
53 div = 1; in get_clocks()
54 pll >>= div; in get_clocks()
59 div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
[all …]
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
66 const struct pll_div *div) in rkclk_set_pll() argument
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
95 (div->postdiv1 << POSTDIV1_SHIFT | in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
[all …]
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| H A D | clk_rk3328.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
207 const struct pll_div *div) in rkclk_set_pll() argument
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
247 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
264 (div->fbdiv << PLL_FBDIV_SHIFT) | in rkclk_set_pll()
265 (div->postdiv1 << PLL_POSTDIV1_SHIFT)); in rkclk_set_pll()
268 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
[all …]
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| H A D | clk_rk3128.c | 27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
39 const struct pll_div *div) in rkclk_set_pll() argument
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
63 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
64 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
76 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config() argument
[all …]
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| H A D | clk_rk3368.c | 41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
89 const struct pll_div *div) in rkclk_set_pll() argument
93 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
94 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
97 pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
104 ((div->nr - 1) << PLL_NR_SHIFT) | in rkclk_set_pll()
105 ((div->no - 1) << PLL_OD_SHIFT)); in rkclk_set_pll()
106 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
111 clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
159 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
[all …]
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 137 unsigned long div; in s5pc110_get_arm_clk() local
141 div = readl(&clk->div0); in s5pc110_get_arm_clk()
144 apll_ratio = div & 0x7; in s5pc110_get_arm_clk()
157 unsigned long div; in s5pc100_get_arm_clk() local
161 div = readl(&clk->div0); in s5pc100_get_arm_clk()
164 arm_ratio = (div >> 4) & 0x7; in s5pc100_get_arm_clk()
166 apll_ratio = div & 0x1; in s5pc100_get_arm_clk()
180 uint div, d0_bus_ratio; in get_hclk() local
182 div = readl(&clk->div0); in get_hclk()
184 d0_bus_ratio = (div >> 8) & 0x7; in get_hclk()
[all …]
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| /openbmc/webui-vue/tests/unit/Global/__snapshots__/ |
| H A D | Search.spec.js.snap | 4 <div
7 <div
19 <div>
20 <div
25 <div
43 </div>
55 </div>
59 </div>
60 </div>
61 </div>
|
| H A D | TableToolbar.spec.js.snap | 7 <div
10 <div
21 <div
33 </div>
34 </div>
35 </div>
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
| H A D | clock.c | 41 uint32_t clkctrl, clkseq, div; in mxs_get_pclk() local
56 div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> in mxs_get_pclk()
58 return XTAL_FREQ_MHZ / div; in mxs_get_pclk()
64 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; in mxs_get_pclk()
65 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_pclk()
73 uint32_t div; in mxs_get_hclk() local
82 div = clkctrl & CLKCTRL_HBUS_DIV_MASK; in mxs_get_hclk()
83 return mxs_get_pclk() / div; in mxs_get_hclk()
91 uint32_t clkctrl, clkseq, div; in mxs_get_emiclk() local
99 div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >> in mxs_get_emiclk()
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| /openbmc/webui-vue/docs/.vuepress/components/colors/ |
| H A D | greens.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="color in colors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| H A D | yellows.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="color in colors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| H A D | blues.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="color in colors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| H A D | reds.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="color in colors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| H A D | all.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="item in baseColors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| H A D | grays.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="color in colors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| H A D | theme.vue | 2 <div>
3 <div class="color-tile-container">
4 <div v-for="item in themeColors">
5 <div
9 ></div>
18 </div>
19 </div>
20 </div>
|
| /openbmc/webui-vue/src/layouts/ |
| H A D | LoginLayout.vue | 3 <div class="login-container">
4 <div class="login-main">
5 <div>
6 <div class="login-brand mb-5">
13 </div>
18 </div>
19 </div>
20 <div class="login-aside">
21 <div class="login-aside__logo-brand">
23 </div>
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| /openbmc/webui-vue/src/components/Global/ |
| H A D | Alert.vue | 3 <div
13 </div>
14 <div class="alert-content">
15 <div class="alert-msg">
17 </div>
18 </div>
19 <div class="alert-action">
21 </div>
|
| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/ |
| H A D | generic.c | 73 ulong div; in imx_get_armclk() local
78 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) in imx_get_armclk()
81 return fref / div; in imx_get_armclk()
89 ulong div; in imx_get_ahbclk() local
91 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) in imx_get_ahbclk()
94 return fref / div; in imx_get_ahbclk()
107 ulong div; in imx_get_perclk() local
109 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); in imx_get_perclk()
110 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; in imx_get_perclk()
112 return fref / div; in imx_get_perclk()
[all …]
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| /openbmc/u-boot/lib/ |
| H A D | tiny-printf.c | 37 unsigned long div) in div_out() argument
41 while (*num >= div) { in div_out()
42 *num -= div; in div_out()
164 unsigned long div; in pointer() local
192 div = 1UL << (sizeof(long) * 8 - 4); in pointer()
193 for (; div; div /= 0x10) in pointer()
194 div_out(info, &num, div); in pointer()
204 unsigned long div; in _vprintf() local
244 div = 1000000000; in _vprintf()
248 div *= div * 10; in _vprintf()
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| /openbmc/u-boot/drivers/clk/mvebu/ |
| H A D | armada-37xx-tbg.c | 57 unsigned int div[NUM_TBG]; member
72 unsigned int div; in tbg_get_div() local
76 div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; in tbg_get_div()
77 if (div == 0) in tbg_get_div()
78 div = 1; in tbg_get_div()
81 div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK); in tbg_get_div()
83 return div; in tbg_get_div()
127 unsigned int mult, div; in armada_37xx_tbg_clk_probe() local
130 div = tbg_get_div(reg, &tbg[i]); in armada_37xx_tbg_clk_probe()
132 priv->rates[i] = (xtal * mult) / div; in armada_37xx_tbg_clk_probe()
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 116 unsigned int div; in exynos_get_pll_clk() local
158 div = PLL_DIV_1024; in exynos_get_pll_clk()
160 div = PLL_DIV_65535; in exynos_get_pll_clk()
163 div = PLL_DIV_65536; in exynos_get_pll_clk()
167 fout = (m + k / div) * (freq / (p * (1 << s))); in exynos_get_pll_clk()
368 unsigned int src = 0, div = 0, sub_div = 0; in exynos5_get_periph_rate() local
378 div = readl(&clk->div_peric0); in exynos5_get_periph_rate()
386 div = readl(&clk->div_peric3); in exynos5_get_periph_rate()
390 div = sub_div = readl(&clk->div_mau); in exynos5_get_periph_rate()
394 div = sub_div = readl(&clk->div_peric1); in exynos5_get_periph_rate()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-core.c | 96 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
112 if (divider_exists(&cd->div)) { in peri_clk_enable()
113 reg = readl(base + cd->div.offset); in peri_clk_enable()
114 bitfield_replace(reg, cd->div.shift, cd->div.width, in peri_clk_enable()
115 c->div - 1); in peri_clk_enable()
116 writel(reg, base + cd->div.offset); in peri_clk_enable()
165 unsigned long new_rate = 0, div = 1; in peri_clk_set_rate() local
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
183 if (div == 0) in peri_clk_set_rate()
184 div = 1; in peri_clk_set_rate()
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-core.c | 96 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
112 if (divider_exists(&cd->div)) { in peri_clk_enable()
113 reg = readl(base + cd->div.offset); in peri_clk_enable()
114 bitfield_replace(reg, cd->div.shift, cd->div.width, in peri_clk_enable()
115 c->div - 1); in peri_clk_enable()
116 writel(reg, base + cd->div.offset); in peri_clk_enable()
165 unsigned long new_rate = 0, div = 1; in peri_clk_set_rate() local
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
183 if (div == 0) in peri_clk_set_rate()
184 div = 1; in peri_clk_set_rate()
[all …]
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