182a248dfSMarek Behún // SPDX-License-Identifier: GPL-2.0+
282a248dfSMarek Behún /*
382a248dfSMarek Behún * Marvell Armada 37xx SoC Time Base Generator clocks
482a248dfSMarek Behún *
582a248dfSMarek Behún * Marek Behun <marek.behun@nic.cz>
682a248dfSMarek Behún *
782a248dfSMarek Behún * Based on Linux driver by:
882a248dfSMarek Behún * Gregory CLEMENT <gregory.clement@free-electrons.com>
982a248dfSMarek Behún */
1082a248dfSMarek Behún
1182a248dfSMarek Behún #include <common.h>
1282a248dfSMarek Behún #include <clk-uclass.h>
1382a248dfSMarek Behún #include <clk.h>
1482a248dfSMarek Behún #include <dm.h>
1582a248dfSMarek Behún #include <asm/io.h>
1682a248dfSMarek Behún #include <asm/arch/cpu.h>
1782a248dfSMarek Behún
1882a248dfSMarek Behún #define NUM_TBG 4
1982a248dfSMarek Behún
2082a248dfSMarek Behún #define TBG_CTRL0 0x4
2182a248dfSMarek Behún #define TBG_CTRL1 0x8
2282a248dfSMarek Behún #define TBG_CTRL7 0x20
2382a248dfSMarek Behún #define TBG_CTRL8 0x30
2482a248dfSMarek Behún
2582a248dfSMarek Behún #define TBG_DIV_MASK 0x1FF
2682a248dfSMarek Behún
2782a248dfSMarek Behún #define TBG_A_REFDIV 0
2882a248dfSMarek Behún #define TBG_B_REFDIV 16
2982a248dfSMarek Behún
3082a248dfSMarek Behún #define TBG_A_FBDIV 2
3182a248dfSMarek Behún #define TBG_B_FBDIV 18
3282a248dfSMarek Behún
3382a248dfSMarek Behún #define TBG_A_VCODIV_SE 0
3482a248dfSMarek Behún #define TBG_B_VCODIV_SE 16
3582a248dfSMarek Behún
3682a248dfSMarek Behún #define TBG_A_VCODIV_DIFF 1
3782a248dfSMarek Behún #define TBG_B_VCODIV_DIFF 17
3882a248dfSMarek Behún
3982a248dfSMarek Behún struct tbg_def {
4082a248dfSMarek Behún const char *name;
4182a248dfSMarek Behún u32 refdiv_offset;
4282a248dfSMarek Behún u32 fbdiv_offset;
4382a248dfSMarek Behún u32 vcodiv_reg;
4482a248dfSMarek Behún u32 vcodiv_offset;
4582a248dfSMarek Behún };
4682a248dfSMarek Behún
4782a248dfSMarek Behún static const struct tbg_def tbg[NUM_TBG] = {
4882a248dfSMarek Behún {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
4982a248dfSMarek Behún {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
5082a248dfSMarek Behún {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
5182a248dfSMarek Behún {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
5282a248dfSMarek Behún };
5382a248dfSMarek Behún
5482a248dfSMarek Behún struct a37xx_tbgclk {
5582a248dfSMarek Behún ulong rates[NUM_TBG];
5682a248dfSMarek Behún unsigned int mult[NUM_TBG];
5782a248dfSMarek Behún unsigned int div[NUM_TBG];
5882a248dfSMarek Behún };
5982a248dfSMarek Behún
tbg_get_mult(void __iomem * reg,const struct tbg_def * ptbg)6082a248dfSMarek Behún static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg)
6182a248dfSMarek Behún {
6282a248dfSMarek Behún u32 val;
6382a248dfSMarek Behún
6482a248dfSMarek Behún val = readl(reg + TBG_CTRL0);
6582a248dfSMarek Behún
6682a248dfSMarek Behún return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2;
6782a248dfSMarek Behún }
6882a248dfSMarek Behún
tbg_get_div(void __iomem * reg,const struct tbg_def * ptbg)6982a248dfSMarek Behún static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg)
7082a248dfSMarek Behún {
7182a248dfSMarek Behún u32 val;
7282a248dfSMarek Behún unsigned int div;
7382a248dfSMarek Behún
7482a248dfSMarek Behún val = readl(reg + TBG_CTRL7);
7582a248dfSMarek Behún
7682a248dfSMarek Behún div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK;
7782a248dfSMarek Behún if (div == 0)
7882a248dfSMarek Behún div = 1;
7982a248dfSMarek Behún val = readl(reg + ptbg->vcodiv_reg);
8082a248dfSMarek Behún
8182a248dfSMarek Behún div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK);
8282a248dfSMarek Behún
8382a248dfSMarek Behún return div;
8482a248dfSMarek Behún }
8582a248dfSMarek Behún
armada_37xx_tbg_clk_get_rate(struct clk * clk)8682a248dfSMarek Behún static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk)
8782a248dfSMarek Behún {
8882a248dfSMarek Behún struct a37xx_tbgclk *priv = dev_get_priv(clk->dev);
8982a248dfSMarek Behún
9082a248dfSMarek Behún if (clk->id >= NUM_TBG)
9182a248dfSMarek Behún return -ENODEV;
9282a248dfSMarek Behún
9382a248dfSMarek Behún return priv->rates[clk->id];
9482a248dfSMarek Behún }
9582a248dfSMarek Behún
96*dd77690cSMarek Behún #if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720)
armada_37xx_tbg_clk_dump(struct udevice * dev)9782a248dfSMarek Behún int armada_37xx_tbg_clk_dump(struct udevice *dev)
9882a248dfSMarek Behún {
9982a248dfSMarek Behún struct a37xx_tbgclk *priv = dev_get_priv(dev);
10082a248dfSMarek Behún int i;
10182a248dfSMarek Behún
10282a248dfSMarek Behún for (i = 0; i < NUM_TBG; ++i)
10382a248dfSMarek Behún printf(" %s at %lu Hz\n", tbg[i].name,
10482a248dfSMarek Behún priv->rates[i]);
10582a248dfSMarek Behún printf("\n");
10682a248dfSMarek Behún
10782a248dfSMarek Behún return 0;
10882a248dfSMarek Behún }
109*dd77690cSMarek Behún #endif
11082a248dfSMarek Behún
armada_37xx_tbg_clk_probe(struct udevice * dev)11182a248dfSMarek Behún static int armada_37xx_tbg_clk_probe(struct udevice *dev)
11282a248dfSMarek Behún {
11382a248dfSMarek Behún struct a37xx_tbgclk *priv = dev_get_priv(dev);
11482a248dfSMarek Behún void __iomem *reg;
11582a248dfSMarek Behún ulong xtal;
11682a248dfSMarek Behún int i;
11782a248dfSMarek Behún
11882a248dfSMarek Behún reg = dev_read_addr_ptr(dev);
11982a248dfSMarek Behún if (!reg) {
12082a248dfSMarek Behún dev_err(dev, "no io address\n");
12182a248dfSMarek Behún return -ENODEV;
12282a248dfSMarek Behún }
12382a248dfSMarek Behún
12482a248dfSMarek Behún xtal = (ulong)get_ref_clk() * 1000000;
12582a248dfSMarek Behún
12682a248dfSMarek Behún for (i = 0; i < NUM_TBG; ++i) {
12782a248dfSMarek Behún unsigned int mult, div;
12882a248dfSMarek Behún
12982a248dfSMarek Behún mult = tbg_get_mult(reg, &tbg[i]);
13082a248dfSMarek Behún div = tbg_get_div(reg, &tbg[i]);
13182a248dfSMarek Behún
13282a248dfSMarek Behún priv->rates[i] = (xtal * mult) / div;
13382a248dfSMarek Behún }
13482a248dfSMarek Behún
13582a248dfSMarek Behún return 0;
13682a248dfSMarek Behún }
13782a248dfSMarek Behún
13882a248dfSMarek Behún static const struct clk_ops armada_37xx_tbg_clk_ops = {
13982a248dfSMarek Behún .get_rate = armada_37xx_tbg_clk_get_rate,
14082a248dfSMarek Behún };
14182a248dfSMarek Behún
14282a248dfSMarek Behún static const struct udevice_id armada_37xx_tbg_clk_ids[] = {
14382a248dfSMarek Behún { .compatible = "marvell,armada-3700-tbg-clock" },
14482a248dfSMarek Behún {}
14582a248dfSMarek Behún };
14682a248dfSMarek Behún
14782a248dfSMarek Behún U_BOOT_DRIVER(armada_37xx_tbg_clk) = {
14882a248dfSMarek Behún .name = "armada_37xx_tbg_clk",
14982a248dfSMarek Behún .id = UCLASS_CLK,
15082a248dfSMarek Behún .of_match = armada_37xx_tbg_clk_ids,
15182a248dfSMarek Behún .ops = &armada_37xx_tbg_clk_ops,
15282a248dfSMarek Behún .priv_auto_alloc_size = sizeof(struct a37xx_tbgclk),
15382a248dfSMarek Behún .probe = armada_37xx_tbg_clk_probe,
15482a248dfSMarek Behún };
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