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Searched refs:disp_dlg_regs (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c857 display_dlg_regs_st *disp_dlg_regs, in dml_rq_dlg_get_dlg_params() argument
967 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml_rq_dlg_get_dlg_params()
990 disp_dlg_regs->min_dst_y_next_start_us = 0; in dml_rq_dlg_get_dlg_params()
1036 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1038 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1041 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1043 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1523 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml_rq_dlg_get_dlg_params()
1524 disp_dlg_regs->dst_y_offset_cur0 = 0; in dml_rq_dlg_get_dlg_params()
1525 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml_rq_dlg_get_dlg_params()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c834 display_dlg_regs_st *disp_dlg_regs, in dml_rq_dlg_get_dlg_params() argument
962 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml_rq_dlg_get_dlg_params()
975 disp_dlg_regs->ref_freq_to_pix_freq = in dml_rq_dlg_get_dlg_params()
1013 disp_dlg_regs->min_dst_y_next_start); in dml_rq_dlg_get_dlg_params()
1081 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1083 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1088 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1613 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml_rq_dlg_get_dlg_params()
1614 disp_dlg_regs->dst_y_offset_cur0 = 0; in dml_rq_dlg_get_dlg_params()
1615 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml_rq_dlg_get_dlg_params()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c894 display_dlg_regs_st *disp_dlg_regs, in dml_rq_dlg_get_dlg_params() argument
1027 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml_rq_dlg_get_dlg_params()
1043 disp_dlg_regs->ref_freq_to_pix_freq = in dml_rq_dlg_get_dlg_params()
1074 disp_dlg_regs->min_dst_y_next_start); in dml_rq_dlg_get_dlg_params()
1139 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1141 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1146 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1698 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml_rq_dlg_get_dlg_params()
1699 disp_dlg_regs->dst_y_offset_cur0 = 0; in dml_rq_dlg_get_dlg_params()
1700 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml_rq_dlg_get_dlg_params()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c942 display_dlg_regs_st *disp_dlg_regs, in dml_rq_dlg_get_dlg_params() argument
1052 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml_rq_dlg_get_dlg_params()
1074 disp_dlg_regs->min_dst_y_next_start_us = in dml_rq_dlg_get_dlg_params()
1123 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1125 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1128 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1130 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1611 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml_rq_dlg_get_dlg_params()
1612 disp_dlg_regs->dst_y_offset_cur0 = 0; in dml_rq_dlg_get_dlg_params()
1613 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml_rq_dlg_get_dlg_params()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c50 display_dlg_regs_st *disp_dlg_regs,
788 display_dlg_regs_st *disp_dlg_regs, in dml20v2_rq_dlg_get_dlg_params() argument
916 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml20v2_rq_dlg_get_dlg_params()
929 disp_dlg_regs->ref_freq_to_pix_freq = in dml20v2_rq_dlg_get_dlg_params()
963 disp_dlg_regs->min_dst_y_next_start); in dml20v2_rq_dlg_get_dlg_params()
1042 disp_dlg_regs->vready_after_vcount0 = 1; in dml20v2_rq_dlg_get_dlg_params()
1044 disp_dlg_regs->vready_after_vcount0 = 0; in dml20v2_rq_dlg_get_dlg_params()
1506 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml20v2_rq_dlg_get_dlg_params()
1507 disp_dlg_regs->dst_y_offset_cur0 = 0; in dml20v2_rq_dlg_get_dlg_params()
1508 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml20v2_rq_dlg_get_dlg_params()
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H A Ddisplay_rq_dlg_calc_20.c50 display_dlg_regs_st *disp_dlg_regs,
788 display_dlg_regs_st *disp_dlg_regs, in dml20_rq_dlg_get_dlg_params() argument
916 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml20_rq_dlg_get_dlg_params()
929 disp_dlg_regs->ref_freq_to_pix_freq = in dml20_rq_dlg_get_dlg_params()
962 disp_dlg_regs->min_dst_y_next_start); in dml20_rq_dlg_get_dlg_params()
1041 disp_dlg_regs->vready_after_vcount0 = 1; in dml20_rq_dlg_get_dlg_params()
1043 disp_dlg_regs->vready_after_vcount0 = 0; in dml20_rq_dlg_get_dlg_params()
1505 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml20_rq_dlg_get_dlg_params()
1506 disp_dlg_regs->dst_y_offset_cur0 = 0; in dml20_rq_dlg_get_dlg_params()
1507 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml20_rq_dlg_get_dlg_params()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c1134 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); in dml1_rq_dlg_get_dlg_params()
1153 disp_dlg_regs->ref_freq_to_pix_freq = in dml1_rq_dlg_get_dlg_params()
1189 disp_dlg_regs->min_dst_y_next_start); in dml1_rq_dlg_get_dlg_params()
1445 disp_dlg_regs->dst_y_after_scaler); in dml1_rq_dlg_get_dlg_params()
1449 disp_dlg_regs->refcyc_x_after_scaler); in dml1_rq_dlg_get_dlg_params()
1455 disp_dlg_regs->dst_y_prefetch); in dml1_rq_dlg_get_dlg_params()
1530 disp_dlg_regs->refcyc_per_pte_group_vblank_l = in dml1_rq_dlg_get_dlg_params()
1535 disp_dlg_regs->refcyc_per_pte_group_vblank_c = in dml1_rq_dlg_get_dlg_params()
1540 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml1_rq_dlg_get_dlg_params()
1737 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml1_rq_dlg_get_dlg_params()
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