Searched refs:dev_specs (Results 1 – 9 of 9) sorted by relevance
1049 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; in hns3_dbg_dev_specs() local1055 dev_specs->mac_entry_num); in hns3_dbg_dev_specs()1057 dev_specs->mng_entry_num); in hns3_dbg_dev_specs()1063 dev_specs->rss_key_size); in hns3_dbg_dev_specs()1081 dev_specs->int_ql_max); in hns3_dbg_dev_specs()1083 dev_specs->max_int_gl); in hns3_dbg_dev_specs()1085 dev_specs->max_tm_rate); in hns3_dbg_dev_specs()1087 dev_specs->max_qset_num); in hns3_dbg_dev_specs()1089 dev_specs->umv_size); in hns3_dbg_dev_specs()1091 dev_specs->mc_mac_size); in hns3_dbg_dev_specs()[all …]
956 return ae_dev->dev_specs.rss_ind_tbl_size; in hns3_get_rss_indir_size()1397 if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) { in hns3_check_gl_coalesce_para()1400 ae_dev->dev_specs.max_int_gl); in hns3_check_gl_coalesce_para()1404 if (cmd->tx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) { in hns3_check_gl_coalesce_para()1407 ae_dev->dev_specs.max_int_gl); in hns3_check_gl_coalesce_para()1469 !ae_dev->dev_specs.int_ql_max) { in hns3_check_ql_coalesce_param()1474 if (cmd->tx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max || in hns3_check_ql_coalesce_param()1475 cmd->rx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max) { in hns3_check_ql_coalesce_param()1478 ae_dev->dev_specs.int_ql_max); in hns3_check_ql_coalesce_param()
414 struct hnae3_dev_specs dev_specs; member
579 if (ae_dev->dev_specs.int_ql_max) { in hns3_vector_coalesce_init()582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; in hns3_vector_coalesce_init()583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; in hns3_vector_coalesce_init()4768 if (ae_dev->dev_specs.int_ql_max) { in hns3_nic_init_coal_cfg()5312 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; in hns3_client_init()5393 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); in hns3_client_init()
545 hdev->ae_dev->dev_specs.rss_ind_tbl_size); in hclgevf_get_rss()2656 ae_dev->dev_specs.max_non_tso_bd_num = in hclgevf_set_default_dev_specs()2675 ae_dev->dev_specs.rss_ind_tbl_size = in hclgevf_parse_dev_specs()2685 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; in hclgevf_check_dev_specs() local2687 if (!dev_specs->max_non_tso_bd_num) in hclgevf_check_dev_specs()2689 if (!dev_specs->rss_ind_tbl_size) in hclgevf_check_dev_specs()2691 if (!dev_specs->rss_key_size) in hclgevf_check_dev_specs()2693 if (!dev_specs->max_int_gl) in hclgevf_check_dev_specs()2694 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; in hclgevf_check_dev_specs()2695 if (!dev_specs->max_frm_size) in hclgevf_check_dev_specs()[all …]
38 u16 rss_ind_tbl_size = ae_dev->dev_specs.rss_ind_tbl_size; in hclge_comm_rss_init_cfg()217 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) in hclge_comm_rss_indir_init_cfg()280 rss_cfg_tbl_num = ae_dev->dev_specs.rss_ind_tbl_size / in hclge_comm_set_rss_indir_table()
1330 ae_dev->dev_specs.tnl_num = 0; in hclge_set_default_dev_specs()1344 ae_dev->dev_specs.rss_ind_tbl_size = in hclge_parse_dev_specs()1359 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; in hclge_check_dev_specs() local1361 if (!dev_specs->max_non_tso_bd_num) in hclge_check_dev_specs()1363 if (!dev_specs->rss_ind_tbl_size) in hclge_check_dev_specs()1365 if (!dev_specs->rss_key_size) in hclge_check_dev_specs()1367 if (!dev_specs->max_tm_rate) in hclge_check_dev_specs()1369 if (!dev_specs->max_qset_num) in hclge_check_dev_specs()1371 if (!dev_specs->max_int_gl) in hclge_check_dev_specs()1373 if (!dev_specs->max_frm_size) in hclge_check_dev_specs()[all …]
474 hdev->ae_dev->dev_specs.max_tm_rate); in hclge_tm_port_shaper_cfg()598 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_qs_shaper_cfg()602 hdev->ae_dev->dev_specs.max_tm_rate); in hclge_tm_qs_shaper_cfg()801 hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pg_info_init()885 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pg_shaper_cfg()1047 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pri_tc_base_shaper_cfg()1098 hdev->ae_dev->dev_specs.max_tm_rate); in hclge_tm_pri_vnet_base_shaper_pri_cfg()1128 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pri_vnet_base_shaper_qs_cfg()
419 HCLGE_REG_TLV_SIZE) * ae_dev->dev_specs.tnl_num; in hclge_get_dfx_reg_len()434 for (i = HCLGE_REG_RPU_TNL_ID_0; i <= ae_dev->dev_specs.tnl_num; i++) { in hclge_get_dfx_rpu_tnl_reg()