1939ccd10SJijie Shao // SPDX-License-Identifier: GPL-2.0+
2939ccd10SJijie Shao // Copyright (c) 2023 Hisilicon Limited.
3939ccd10SJijie Shao
4939ccd10SJijie Shao #include "hclge_cmd.h"
5939ccd10SJijie Shao #include "hclge_main.h"
6939ccd10SJijie Shao #include "hclge_regs.h"
7939ccd10SJijie Shao #include "hnae3.h"
8939ccd10SJijie Shao
9939ccd10SJijie Shao static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
10939ccd10SJijie Shao HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
11939ccd10SJijie Shao HCLGE_COMM_NIC_CSQ_DEPTH_REG,
12939ccd10SJijie Shao HCLGE_COMM_NIC_CSQ_TAIL_REG,
13939ccd10SJijie Shao HCLGE_COMM_NIC_CSQ_HEAD_REG,
14939ccd10SJijie Shao HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
15939ccd10SJijie Shao HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
16939ccd10SJijie Shao HCLGE_COMM_NIC_CRQ_DEPTH_REG,
17939ccd10SJijie Shao HCLGE_COMM_NIC_CRQ_TAIL_REG,
18939ccd10SJijie Shao HCLGE_COMM_NIC_CRQ_HEAD_REG,
19939ccd10SJijie Shao HCLGE_COMM_VECTOR0_CMDQ_SRC_REG,
20939ccd10SJijie Shao HCLGE_COMM_CMDQ_INTR_STS_REG,
21939ccd10SJijie Shao HCLGE_COMM_CMDQ_INTR_EN_REG,
22939ccd10SJijie Shao HCLGE_COMM_CMDQ_INTR_GEN_REG};
23939ccd10SJijie Shao
24939ccd10SJijie Shao static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
25939ccd10SJijie Shao HCLGE_PF_OTHER_INT_REG,
26939ccd10SJijie Shao HCLGE_MISC_RESET_STS_REG,
27939ccd10SJijie Shao HCLGE_MISC_VECTOR_INT_STS,
28939ccd10SJijie Shao HCLGE_GLOBAL_RESET_REG,
29939ccd10SJijie Shao HCLGE_FUN_RST_ING,
30939ccd10SJijie Shao HCLGE_GRO_EN_REG};
31939ccd10SJijie Shao
32939ccd10SJijie Shao static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
33939ccd10SJijie Shao HCLGE_RING_RX_ADDR_H_REG,
34939ccd10SJijie Shao HCLGE_RING_RX_BD_NUM_REG,
35939ccd10SJijie Shao HCLGE_RING_RX_BD_LENGTH_REG,
36939ccd10SJijie Shao HCLGE_RING_RX_MERGE_EN_REG,
37939ccd10SJijie Shao HCLGE_RING_RX_TAIL_REG,
38939ccd10SJijie Shao HCLGE_RING_RX_HEAD_REG,
39939ccd10SJijie Shao HCLGE_RING_RX_FBD_NUM_REG,
40939ccd10SJijie Shao HCLGE_RING_RX_OFFSET_REG,
41939ccd10SJijie Shao HCLGE_RING_RX_FBD_OFFSET_REG,
42939ccd10SJijie Shao HCLGE_RING_RX_STASH_REG,
43939ccd10SJijie Shao HCLGE_RING_RX_BD_ERR_REG,
44939ccd10SJijie Shao HCLGE_RING_TX_ADDR_L_REG,
45939ccd10SJijie Shao HCLGE_RING_TX_ADDR_H_REG,
46939ccd10SJijie Shao HCLGE_RING_TX_BD_NUM_REG,
47939ccd10SJijie Shao HCLGE_RING_TX_PRIORITY_REG,
48939ccd10SJijie Shao HCLGE_RING_TX_TC_REG,
49939ccd10SJijie Shao HCLGE_RING_TX_MERGE_EN_REG,
50939ccd10SJijie Shao HCLGE_RING_TX_TAIL_REG,
51939ccd10SJijie Shao HCLGE_RING_TX_HEAD_REG,
52939ccd10SJijie Shao HCLGE_RING_TX_FBD_NUM_REG,
53939ccd10SJijie Shao HCLGE_RING_TX_OFFSET_REG,
54939ccd10SJijie Shao HCLGE_RING_TX_EBD_NUM_REG,
55939ccd10SJijie Shao HCLGE_RING_TX_EBD_OFFSET_REG,
56939ccd10SJijie Shao HCLGE_RING_TX_BD_ERR_REG,
57939ccd10SJijie Shao HCLGE_RING_EN_REG};
58939ccd10SJijie Shao
59939ccd10SJijie Shao static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
60939ccd10SJijie Shao HCLGE_TQP_INTR_GL0_REG,
61939ccd10SJijie Shao HCLGE_TQP_INTR_GL1_REG,
62939ccd10SJijie Shao HCLGE_TQP_INTR_GL2_REG,
63939ccd10SJijie Shao HCLGE_TQP_INTR_RL_REG};
64939ccd10SJijie Shao
65939ccd10SJijie Shao /* Get DFX BD number offset */
66939ccd10SJijie Shao #define HCLGE_DFX_BIOS_BD_OFFSET 1
67939ccd10SJijie Shao #define HCLGE_DFX_SSU_0_BD_OFFSET 2
68939ccd10SJijie Shao #define HCLGE_DFX_SSU_1_BD_OFFSET 3
69939ccd10SJijie Shao #define HCLGE_DFX_IGU_BD_OFFSET 4
70939ccd10SJijie Shao #define HCLGE_DFX_RPU_0_BD_OFFSET 5
71939ccd10SJijie Shao #define HCLGE_DFX_RPU_1_BD_OFFSET 6
72939ccd10SJijie Shao #define HCLGE_DFX_NCSI_BD_OFFSET 7
73939ccd10SJijie Shao #define HCLGE_DFX_RTC_BD_OFFSET 8
74939ccd10SJijie Shao #define HCLGE_DFX_PPP_BD_OFFSET 9
75939ccd10SJijie Shao #define HCLGE_DFX_RCB_BD_OFFSET 10
76939ccd10SJijie Shao #define HCLGE_DFX_TQP_BD_OFFSET 11
77939ccd10SJijie Shao #define HCLGE_DFX_SSU_2_BD_OFFSET 12
78939ccd10SJijie Shao
79939ccd10SJijie Shao static const u32 hclge_dfx_bd_offset_list[] = {
80939ccd10SJijie Shao HCLGE_DFX_BIOS_BD_OFFSET,
81939ccd10SJijie Shao HCLGE_DFX_SSU_0_BD_OFFSET,
82939ccd10SJijie Shao HCLGE_DFX_SSU_1_BD_OFFSET,
83939ccd10SJijie Shao HCLGE_DFX_IGU_BD_OFFSET,
84939ccd10SJijie Shao HCLGE_DFX_RPU_0_BD_OFFSET,
85939ccd10SJijie Shao HCLGE_DFX_RPU_1_BD_OFFSET,
86939ccd10SJijie Shao HCLGE_DFX_NCSI_BD_OFFSET,
87939ccd10SJijie Shao HCLGE_DFX_RTC_BD_OFFSET,
88939ccd10SJijie Shao HCLGE_DFX_PPP_BD_OFFSET,
89939ccd10SJijie Shao HCLGE_DFX_RCB_BD_OFFSET,
90939ccd10SJijie Shao HCLGE_DFX_TQP_BD_OFFSET,
91939ccd10SJijie Shao HCLGE_DFX_SSU_2_BD_OFFSET
92939ccd10SJijie Shao };
93939ccd10SJijie Shao
94939ccd10SJijie Shao static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = {
95939ccd10SJijie Shao HCLGE_OPC_DFX_BIOS_COMMON_REG,
96939ccd10SJijie Shao HCLGE_OPC_DFX_SSU_REG_0,
97939ccd10SJijie Shao HCLGE_OPC_DFX_SSU_REG_1,
98939ccd10SJijie Shao HCLGE_OPC_DFX_IGU_EGU_REG,
99939ccd10SJijie Shao HCLGE_OPC_DFX_RPU_REG_0,
100939ccd10SJijie Shao HCLGE_OPC_DFX_RPU_REG_1,
101939ccd10SJijie Shao HCLGE_OPC_DFX_NCSI_REG,
102939ccd10SJijie Shao HCLGE_OPC_DFX_RTC_REG,
103939ccd10SJijie Shao HCLGE_OPC_DFX_PPP_REG,
104939ccd10SJijie Shao HCLGE_OPC_DFX_RCB_REG,
105939ccd10SJijie Shao HCLGE_OPC_DFX_TQP_REG,
106939ccd10SJijie Shao HCLGE_OPC_DFX_SSU_REG_2
107939ccd10SJijie Shao };
108939ccd10SJijie Shao
109d8634b7cSJijie Shao enum hclge_reg_tag {
110d8634b7cSJijie Shao HCLGE_REG_TAG_CMDQ = 0,
111d8634b7cSJijie Shao HCLGE_REG_TAG_COMMON,
112d8634b7cSJijie Shao HCLGE_REG_TAG_RING,
113d8634b7cSJijie Shao HCLGE_REG_TAG_TQP_INTR,
114d8634b7cSJijie Shao HCLGE_REG_TAG_QUERY_32_BIT,
115d8634b7cSJijie Shao HCLGE_REG_TAG_QUERY_64_BIT,
116d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_BIOS_COMMON,
117d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_SSU_0,
118d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_SSU_1,
119d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_IGU_EGU,
120d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_RPU_0,
121d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_RPU_1,
122d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_NCSI,
123d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_RTC,
124d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_PPP,
125d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_RCB,
126d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_TQP,
127d8634b7cSJijie Shao HCLGE_REG_TAG_DFX_SSU_2,
128*36122201SJijie Shao HCLGE_REG_TAG_RPU_TNL,
129d8634b7cSJijie Shao };
130d8634b7cSJijie Shao
131d8634b7cSJijie Shao #pragma pack(4)
132d8634b7cSJijie Shao struct hclge_reg_tlv {
133d8634b7cSJijie Shao u16 tag;
134d8634b7cSJijie Shao u16 len;
135d8634b7cSJijie Shao };
136d8634b7cSJijie Shao
137d8634b7cSJijie Shao struct hclge_reg_header {
138d8634b7cSJijie Shao u64 magic_number;
139d8634b7cSJijie Shao u8 is_vf;
140d8634b7cSJijie Shao u8 rsv[7];
141d8634b7cSJijie Shao };
142d8634b7cSJijie Shao
143d8634b7cSJijie Shao #pragma pack()
144d8634b7cSJijie Shao
145d8634b7cSJijie Shao #define HCLGE_REG_TLV_SIZE sizeof(struct hclge_reg_tlv)
146d8634b7cSJijie Shao #define HCLGE_REG_HEADER_SIZE sizeof(struct hclge_reg_header)
147d8634b7cSJijie Shao #define HCLGE_REG_TLV_SPACE (sizeof(struct hclge_reg_tlv) / sizeof(u32))
148d8634b7cSJijie Shao #define HCLGE_REG_HEADER_SPACE (sizeof(struct hclge_reg_header) / sizeof(u32))
149d8634b7cSJijie Shao #define HCLGE_REG_MAGIC_NUMBER 0x686e733372656773 /* meaning is hns3regs */
150d8634b7cSJijie Shao
151*36122201SJijie Shao #define HCLGE_REG_RPU_TNL_ID_0 1
152*36122201SJijie Shao
hclge_reg_get_header(void * data)153d8634b7cSJijie Shao static u32 hclge_reg_get_header(void *data)
154d8634b7cSJijie Shao {
155d8634b7cSJijie Shao struct hclge_reg_header *header = data;
156d8634b7cSJijie Shao
157d8634b7cSJijie Shao header->magic_number = HCLGE_REG_MAGIC_NUMBER;
158d8634b7cSJijie Shao header->is_vf = 0x0;
159d8634b7cSJijie Shao
160d8634b7cSJijie Shao return HCLGE_REG_HEADER_SPACE;
161d8634b7cSJijie Shao }
162d8634b7cSJijie Shao
hclge_reg_get_tlv(u32 tag,u32 regs_num,void * data)163d8634b7cSJijie Shao static u32 hclge_reg_get_tlv(u32 tag, u32 regs_num, void *data)
164d8634b7cSJijie Shao {
165d8634b7cSJijie Shao struct hclge_reg_tlv *tlv = data;
166d8634b7cSJijie Shao
167d8634b7cSJijie Shao tlv->tag = tag;
168d8634b7cSJijie Shao tlv->len = regs_num * sizeof(u32) + HCLGE_REG_TLV_SIZE;
169d8634b7cSJijie Shao
170d8634b7cSJijie Shao return HCLGE_REG_TLV_SPACE;
171d8634b7cSJijie Shao }
172939ccd10SJijie Shao
hclge_get_32_bit_regs(struct hclge_dev * hdev,u32 regs_num,void * data)173939ccd10SJijie Shao static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
174939ccd10SJijie Shao void *data)
175939ccd10SJijie Shao {
176939ccd10SJijie Shao #define HCLGE_32_BIT_REG_RTN_DATANUM 8
177939ccd10SJijie Shao #define HCLGE_32_BIT_DESC_NODATA_LEN 2
178939ccd10SJijie Shao
179939ccd10SJijie Shao struct hclge_desc *desc;
180939ccd10SJijie Shao u32 *reg_val = data;
181939ccd10SJijie Shao __le32 *desc_data;
182939ccd10SJijie Shao int nodata_num;
183939ccd10SJijie Shao int cmd_num;
184939ccd10SJijie Shao int i, k, n;
185939ccd10SJijie Shao int ret;
186939ccd10SJijie Shao
187939ccd10SJijie Shao if (regs_num == 0)
188939ccd10SJijie Shao return 0;
189939ccd10SJijie Shao
190939ccd10SJijie Shao nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN;
191939ccd10SJijie Shao cmd_num = DIV_ROUND_UP(regs_num + nodata_num,
192939ccd10SJijie Shao HCLGE_32_BIT_REG_RTN_DATANUM);
193939ccd10SJijie Shao desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
194939ccd10SJijie Shao if (!desc)
195939ccd10SJijie Shao return -ENOMEM;
196939ccd10SJijie Shao
197939ccd10SJijie Shao hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
198939ccd10SJijie Shao ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
199939ccd10SJijie Shao if (ret) {
200939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
201939ccd10SJijie Shao "Query 32 bit register cmd failed, ret = %d.\n", ret);
202939ccd10SJijie Shao kfree(desc);
203939ccd10SJijie Shao return ret;
204939ccd10SJijie Shao }
205939ccd10SJijie Shao
206939ccd10SJijie Shao for (i = 0; i < cmd_num; i++) {
207939ccd10SJijie Shao if (i == 0) {
208939ccd10SJijie Shao desc_data = (__le32 *)(&desc[i].data[0]);
209939ccd10SJijie Shao n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num;
210939ccd10SJijie Shao } else {
211939ccd10SJijie Shao desc_data = (__le32 *)(&desc[i]);
212939ccd10SJijie Shao n = HCLGE_32_BIT_REG_RTN_DATANUM;
213939ccd10SJijie Shao }
214939ccd10SJijie Shao for (k = 0; k < n; k++) {
215939ccd10SJijie Shao *reg_val++ = le32_to_cpu(*desc_data++);
216939ccd10SJijie Shao
217939ccd10SJijie Shao regs_num--;
218939ccd10SJijie Shao if (!regs_num)
219939ccd10SJijie Shao break;
220939ccd10SJijie Shao }
221939ccd10SJijie Shao }
222939ccd10SJijie Shao
223939ccd10SJijie Shao kfree(desc);
224939ccd10SJijie Shao return 0;
225939ccd10SJijie Shao }
226939ccd10SJijie Shao
hclge_get_64_bit_regs(struct hclge_dev * hdev,u32 regs_num,void * data)227939ccd10SJijie Shao static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
228939ccd10SJijie Shao void *data)
229939ccd10SJijie Shao {
230939ccd10SJijie Shao #define HCLGE_64_BIT_REG_RTN_DATANUM 4
231939ccd10SJijie Shao #define HCLGE_64_BIT_DESC_NODATA_LEN 1
232939ccd10SJijie Shao
233939ccd10SJijie Shao struct hclge_desc *desc;
234939ccd10SJijie Shao u64 *reg_val = data;
235939ccd10SJijie Shao __le64 *desc_data;
236939ccd10SJijie Shao int nodata_len;
237939ccd10SJijie Shao int cmd_num;
238939ccd10SJijie Shao int i, k, n;
239939ccd10SJijie Shao int ret;
240939ccd10SJijie Shao
241939ccd10SJijie Shao if (regs_num == 0)
242939ccd10SJijie Shao return 0;
243939ccd10SJijie Shao
244939ccd10SJijie Shao nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN;
245939ccd10SJijie Shao cmd_num = DIV_ROUND_UP(regs_num + nodata_len,
246939ccd10SJijie Shao HCLGE_64_BIT_REG_RTN_DATANUM);
247939ccd10SJijie Shao desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
248939ccd10SJijie Shao if (!desc)
249939ccd10SJijie Shao return -ENOMEM;
250939ccd10SJijie Shao
251939ccd10SJijie Shao hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
252939ccd10SJijie Shao ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
253939ccd10SJijie Shao if (ret) {
254939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
255939ccd10SJijie Shao "Query 64 bit register cmd failed, ret = %d.\n", ret);
256939ccd10SJijie Shao kfree(desc);
257939ccd10SJijie Shao return ret;
258939ccd10SJijie Shao }
259939ccd10SJijie Shao
260939ccd10SJijie Shao for (i = 0; i < cmd_num; i++) {
261939ccd10SJijie Shao if (i == 0) {
262939ccd10SJijie Shao desc_data = (__le64 *)(&desc[i].data[0]);
263939ccd10SJijie Shao n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len;
264939ccd10SJijie Shao } else {
265939ccd10SJijie Shao desc_data = (__le64 *)(&desc[i]);
266939ccd10SJijie Shao n = HCLGE_64_BIT_REG_RTN_DATANUM;
267939ccd10SJijie Shao }
268939ccd10SJijie Shao for (k = 0; k < n; k++) {
269939ccd10SJijie Shao *reg_val++ = le64_to_cpu(*desc_data++);
270939ccd10SJijie Shao
271939ccd10SJijie Shao regs_num--;
272939ccd10SJijie Shao if (!regs_num)
273939ccd10SJijie Shao break;
274939ccd10SJijie Shao }
275939ccd10SJijie Shao }
276939ccd10SJijie Shao
277939ccd10SJijie Shao kfree(desc);
278939ccd10SJijie Shao return 0;
279939ccd10SJijie Shao }
280939ccd10SJijie Shao
hclge_query_bd_num_cmd_send(struct hclge_dev * hdev,struct hclge_desc * desc)281939ccd10SJijie Shao int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc)
282939ccd10SJijie Shao {
283939ccd10SJijie Shao int i;
284939ccd10SJijie Shao
285939ccd10SJijie Shao /* initialize command BD except the last one */
286939ccd10SJijie Shao for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) {
287939ccd10SJijie Shao hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM,
288939ccd10SJijie Shao true);
289939ccd10SJijie Shao desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
290939ccd10SJijie Shao }
291939ccd10SJijie Shao
292939ccd10SJijie Shao /* initialize the last command BD */
293939ccd10SJijie Shao hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true);
294939ccd10SJijie Shao
295939ccd10SJijie Shao return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT);
296939ccd10SJijie Shao }
297939ccd10SJijie Shao
hclge_get_dfx_reg_bd_num(struct hclge_dev * hdev,int * bd_num_list,u32 type_num)298939ccd10SJijie Shao static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev,
299939ccd10SJijie Shao int *bd_num_list,
300939ccd10SJijie Shao u32 type_num)
301939ccd10SJijie Shao {
302939ccd10SJijie Shao u32 entries_per_desc, desc_index, index, offset, i;
303939ccd10SJijie Shao struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT];
304939ccd10SJijie Shao int ret;
305939ccd10SJijie Shao
306939ccd10SJijie Shao ret = hclge_query_bd_num_cmd_send(hdev, desc);
307939ccd10SJijie Shao if (ret) {
308939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
309939ccd10SJijie Shao "Get dfx bd num fail, status is %d.\n", ret);
310939ccd10SJijie Shao return ret;
311939ccd10SJijie Shao }
312939ccd10SJijie Shao
313939ccd10SJijie Shao entries_per_desc = ARRAY_SIZE(desc[0].data);
314939ccd10SJijie Shao for (i = 0; i < type_num; i++) {
315939ccd10SJijie Shao offset = hclge_dfx_bd_offset_list[i];
316939ccd10SJijie Shao index = offset % entries_per_desc;
317939ccd10SJijie Shao desc_index = offset / entries_per_desc;
318939ccd10SJijie Shao bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]);
319939ccd10SJijie Shao }
320939ccd10SJijie Shao
321939ccd10SJijie Shao return ret;
322939ccd10SJijie Shao }
323939ccd10SJijie Shao
hclge_dfx_reg_cmd_send(struct hclge_dev * hdev,struct hclge_desc * desc_src,int bd_num,enum hclge_opcode_type cmd)324939ccd10SJijie Shao static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev,
325939ccd10SJijie Shao struct hclge_desc *desc_src, int bd_num,
326939ccd10SJijie Shao enum hclge_opcode_type cmd)
327939ccd10SJijie Shao {
328939ccd10SJijie Shao struct hclge_desc *desc = desc_src;
329939ccd10SJijie Shao int i, ret;
330939ccd10SJijie Shao
331939ccd10SJijie Shao hclge_cmd_setup_basic_desc(desc, cmd, true);
332939ccd10SJijie Shao for (i = 0; i < bd_num - 1; i++) {
333939ccd10SJijie Shao desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
334939ccd10SJijie Shao desc++;
335939ccd10SJijie Shao hclge_cmd_setup_basic_desc(desc, cmd, true);
336939ccd10SJijie Shao }
337939ccd10SJijie Shao
338939ccd10SJijie Shao desc = desc_src;
339939ccd10SJijie Shao ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
340939ccd10SJijie Shao if (ret)
341939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
342939ccd10SJijie Shao "Query dfx reg cmd(0x%x) send fail, status is %d.\n",
343939ccd10SJijie Shao cmd, ret);
344939ccd10SJijie Shao
345939ccd10SJijie Shao return ret;
346939ccd10SJijie Shao }
347939ccd10SJijie Shao
348*36122201SJijie Shao /* tnl_id = 0 means get sum of all tnl reg's value */
hclge_dfx_reg_rpu_tnl_cmd_send(struct hclge_dev * hdev,u32 tnl_id,struct hclge_desc * desc,int bd_num)349*36122201SJijie Shao static int hclge_dfx_reg_rpu_tnl_cmd_send(struct hclge_dev *hdev, u32 tnl_id,
350*36122201SJijie Shao struct hclge_desc *desc, int bd_num)
351*36122201SJijie Shao {
352*36122201SJijie Shao int i, ret;
353*36122201SJijie Shao
354*36122201SJijie Shao for (i = 0; i < bd_num; i++) {
355*36122201SJijie Shao hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_RPU_REG_0,
356*36122201SJijie Shao true);
357*36122201SJijie Shao if (i != bd_num - 1)
358*36122201SJijie Shao desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
359*36122201SJijie Shao }
360*36122201SJijie Shao
361*36122201SJijie Shao desc[0].data[0] = cpu_to_le32(tnl_id);
362*36122201SJijie Shao ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
363*36122201SJijie Shao if (ret)
364*36122201SJijie Shao dev_err(&hdev->pdev->dev,
365*36122201SJijie Shao "failed to query dfx rpu tnl reg, ret = %d\n",
366*36122201SJijie Shao ret);
367*36122201SJijie Shao return ret;
368*36122201SJijie Shao }
369*36122201SJijie Shao
hclge_dfx_reg_fetch_data(struct hclge_desc * desc_src,int bd_num,void * data)370939ccd10SJijie Shao static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num,
371939ccd10SJijie Shao void *data)
372939ccd10SJijie Shao {
373d8634b7cSJijie Shao int entries_per_desc, reg_num, desc_index, index, i;
374939ccd10SJijie Shao struct hclge_desc *desc = desc_src;
375939ccd10SJijie Shao u32 *reg = data;
376939ccd10SJijie Shao
377939ccd10SJijie Shao entries_per_desc = ARRAY_SIZE(desc->data);
378939ccd10SJijie Shao reg_num = entries_per_desc * bd_num;
379939ccd10SJijie Shao for (i = 0; i < reg_num; i++) {
380939ccd10SJijie Shao index = i % entries_per_desc;
381939ccd10SJijie Shao desc_index = i / entries_per_desc;
382939ccd10SJijie Shao *reg++ = le32_to_cpu(desc[desc_index].data[index]);
383939ccd10SJijie Shao }
384939ccd10SJijie Shao
385d8634b7cSJijie Shao return reg_num;
386939ccd10SJijie Shao }
387939ccd10SJijie Shao
hclge_get_dfx_reg_len(struct hclge_dev * hdev,int * len)388939ccd10SJijie Shao static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len)
389939ccd10SJijie Shao {
390939ccd10SJijie Shao u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list);
391*36122201SJijie Shao struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
392d8634b7cSJijie Shao int data_len_per_desc;
393939ccd10SJijie Shao int *bd_num_list;
394939ccd10SJijie Shao int ret;
395d8634b7cSJijie Shao u32 i;
396939ccd10SJijie Shao
397939ccd10SJijie Shao bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL);
398939ccd10SJijie Shao if (!bd_num_list)
399939ccd10SJijie Shao return -ENOMEM;
400939ccd10SJijie Shao
401939ccd10SJijie Shao ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num);
402939ccd10SJijie Shao if (ret) {
403939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
404939ccd10SJijie Shao "Get dfx reg bd num fail, status is %d.\n", ret);
405939ccd10SJijie Shao goto out;
406939ccd10SJijie Shao }
407939ccd10SJijie Shao
408939ccd10SJijie Shao data_len_per_desc = sizeof_field(struct hclge_desc, data);
409939ccd10SJijie Shao *len = 0;
410d8634b7cSJijie Shao for (i = 0; i < dfx_reg_type_num; i++)
411d8634b7cSJijie Shao *len += bd_num_list[i] * data_len_per_desc + HCLGE_REG_TLV_SIZE;
412939ccd10SJijie Shao
413*36122201SJijie Shao /**
414*36122201SJijie Shao * the num of dfx_rpu_0 is reused by each dfx_rpu_tnl
415*36122201SJijie Shao * HCLGE_DFX_BD_OFFSET is starting at 1, but the array subscript is
416*36122201SJijie Shao * starting at 0, so offset need '- 1'.
417*36122201SJijie Shao */
418*36122201SJijie Shao *len += (bd_num_list[HCLGE_DFX_RPU_0_BD_OFFSET - 1] * data_len_per_desc +
419*36122201SJijie Shao HCLGE_REG_TLV_SIZE) * ae_dev->dev_specs.tnl_num;
420*36122201SJijie Shao
421939ccd10SJijie Shao out:
422939ccd10SJijie Shao kfree(bd_num_list);
423939ccd10SJijie Shao return ret;
424939ccd10SJijie Shao }
425939ccd10SJijie Shao
hclge_get_dfx_rpu_tnl_reg(struct hclge_dev * hdev,u32 * reg,struct hclge_desc * desc_src,int bd_num)426*36122201SJijie Shao static int hclge_get_dfx_rpu_tnl_reg(struct hclge_dev *hdev, u32 *reg,
427*36122201SJijie Shao struct hclge_desc *desc_src,
428*36122201SJijie Shao int bd_num)
429*36122201SJijie Shao {
430*36122201SJijie Shao struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
431*36122201SJijie Shao int ret = 0;
432*36122201SJijie Shao u8 i;
433*36122201SJijie Shao
434*36122201SJijie Shao for (i = HCLGE_REG_RPU_TNL_ID_0; i <= ae_dev->dev_specs.tnl_num; i++) {
435*36122201SJijie Shao ret = hclge_dfx_reg_rpu_tnl_cmd_send(hdev, i, desc_src, bd_num);
436*36122201SJijie Shao if (ret)
437*36122201SJijie Shao break;
438*36122201SJijie Shao
439*36122201SJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_RPU_TNL,
440*36122201SJijie Shao ARRAY_SIZE(desc_src->data) * bd_num,
441*36122201SJijie Shao reg);
442*36122201SJijie Shao reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg);
443*36122201SJijie Shao }
444*36122201SJijie Shao
445*36122201SJijie Shao return ret;
446*36122201SJijie Shao }
447*36122201SJijie Shao
hclge_get_dfx_reg(struct hclge_dev * hdev,void * data)448939ccd10SJijie Shao static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data)
449939ccd10SJijie Shao {
450939ccd10SJijie Shao u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list);
451939ccd10SJijie Shao int bd_num, bd_num_max, buf_len;
452939ccd10SJijie Shao struct hclge_desc *desc_src;
453939ccd10SJijie Shao int *bd_num_list;
454939ccd10SJijie Shao u32 *reg = data;
455939ccd10SJijie Shao int ret;
456939ccd10SJijie Shao u32 i;
457939ccd10SJijie Shao
458939ccd10SJijie Shao bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL);
459939ccd10SJijie Shao if (!bd_num_list)
460939ccd10SJijie Shao return -ENOMEM;
461939ccd10SJijie Shao
462939ccd10SJijie Shao ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num);
463939ccd10SJijie Shao if (ret) {
464939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
465939ccd10SJijie Shao "Get dfx reg bd num fail, status is %d.\n", ret);
466939ccd10SJijie Shao goto out;
467939ccd10SJijie Shao }
468939ccd10SJijie Shao
469939ccd10SJijie Shao bd_num_max = bd_num_list[0];
470939ccd10SJijie Shao for (i = 1; i < dfx_reg_type_num; i++)
471939ccd10SJijie Shao bd_num_max = max_t(int, bd_num_max, bd_num_list[i]);
472939ccd10SJijie Shao
473939ccd10SJijie Shao buf_len = sizeof(*desc_src) * bd_num_max;
474939ccd10SJijie Shao desc_src = kzalloc(buf_len, GFP_KERNEL);
475939ccd10SJijie Shao if (!desc_src) {
476939ccd10SJijie Shao ret = -ENOMEM;
477939ccd10SJijie Shao goto out;
478939ccd10SJijie Shao }
479939ccd10SJijie Shao
480939ccd10SJijie Shao for (i = 0; i < dfx_reg_type_num; i++) {
481939ccd10SJijie Shao bd_num = bd_num_list[i];
482939ccd10SJijie Shao ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num,
483939ccd10SJijie Shao hclge_dfx_reg_opcode_list[i]);
484939ccd10SJijie Shao if (ret) {
485939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
486939ccd10SJijie Shao "Get dfx reg fail, status is %d.\n", ret);
487*36122201SJijie Shao goto free;
488939ccd10SJijie Shao }
489939ccd10SJijie Shao
490d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_DFX_BIOS_COMMON + i,
491d8634b7cSJijie Shao ARRAY_SIZE(desc_src->data) * bd_num,
492d8634b7cSJijie Shao reg);
493939ccd10SJijie Shao reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg);
494939ccd10SJijie Shao }
495939ccd10SJijie Shao
496*36122201SJijie Shao /**
497*36122201SJijie Shao * HCLGE_DFX_BD_OFFSET is starting at 1, but the array subscript is
498*36122201SJijie Shao * starting at 0, so offset need '- 1'.
499*36122201SJijie Shao */
500*36122201SJijie Shao bd_num = bd_num_list[HCLGE_DFX_RPU_0_BD_OFFSET - 1];
501*36122201SJijie Shao ret = hclge_get_dfx_rpu_tnl_reg(hdev, reg, desc_src, bd_num);
502*36122201SJijie Shao
503*36122201SJijie Shao free:
504939ccd10SJijie Shao kfree(desc_src);
505939ccd10SJijie Shao out:
506939ccd10SJijie Shao kfree(bd_num_list);
507939ccd10SJijie Shao return ret;
508939ccd10SJijie Shao }
509939ccd10SJijie Shao
hclge_fetch_pf_reg(struct hclge_dev * hdev,void * data,struct hnae3_knic_private_info * kinfo)510939ccd10SJijie Shao static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data,
511939ccd10SJijie Shao struct hnae3_knic_private_info *kinfo)
512939ccd10SJijie Shao {
513939ccd10SJijie Shao #define HCLGE_RING_REG_OFFSET 0x200
514939ccd10SJijie Shao #define HCLGE_RING_INT_REG_OFFSET 0x4
515939ccd10SJijie Shao
516d8634b7cSJijie Shao int i, j, reg_num;
517939ccd10SJijie Shao int data_num_sum;
518939ccd10SJijie Shao u32 *reg = data;
519939ccd10SJijie Shao
520939ccd10SJijie Shao /* fetching per-PF registers valus from PF PCIe register space */
521939ccd10SJijie Shao reg_num = ARRAY_SIZE(cmdq_reg_addr_list);
522d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_CMDQ, reg_num, reg);
523939ccd10SJijie Shao for (i = 0; i < reg_num; i++)
524939ccd10SJijie Shao *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
525d8634b7cSJijie Shao data_num_sum = reg_num + HCLGE_REG_TLV_SPACE;
526939ccd10SJijie Shao
527939ccd10SJijie Shao reg_num = ARRAY_SIZE(common_reg_addr_list);
528d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_COMMON, reg_num, reg);
529939ccd10SJijie Shao for (i = 0; i < reg_num; i++)
530939ccd10SJijie Shao *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
531d8634b7cSJijie Shao data_num_sum += reg_num + HCLGE_REG_TLV_SPACE;
532939ccd10SJijie Shao
533939ccd10SJijie Shao reg_num = ARRAY_SIZE(ring_reg_addr_list);
534939ccd10SJijie Shao for (j = 0; j < kinfo->num_tqps; j++) {
535d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_RING, reg_num, reg);
536939ccd10SJijie Shao for (i = 0; i < reg_num; i++)
537939ccd10SJijie Shao *reg++ = hclge_read_dev(&hdev->hw,
538939ccd10SJijie Shao ring_reg_addr_list[i] +
539939ccd10SJijie Shao HCLGE_RING_REG_OFFSET * j);
540939ccd10SJijie Shao }
541d8634b7cSJijie Shao data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) * kinfo->num_tqps;
542939ccd10SJijie Shao
543939ccd10SJijie Shao reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list);
544939ccd10SJijie Shao for (j = 0; j < hdev->num_msi_used - 1; j++) {
545d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_TQP_INTR, reg_num, reg);
546939ccd10SJijie Shao for (i = 0; i < reg_num; i++)
547939ccd10SJijie Shao *reg++ = hclge_read_dev(&hdev->hw,
548939ccd10SJijie Shao tqp_intr_reg_addr_list[i] +
549939ccd10SJijie Shao HCLGE_RING_INT_REG_OFFSET * j);
550939ccd10SJijie Shao }
551d8634b7cSJijie Shao data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) *
552d8634b7cSJijie Shao (hdev->num_msi_used - 1);
553939ccd10SJijie Shao
554939ccd10SJijie Shao return data_num_sum;
555939ccd10SJijie Shao }
556939ccd10SJijie Shao
hclge_get_regs_num(struct hclge_dev * hdev,u32 * regs_num_32_bit,u32 * regs_num_64_bit)557939ccd10SJijie Shao static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
558939ccd10SJijie Shao u32 *regs_num_64_bit)
559939ccd10SJijie Shao {
560939ccd10SJijie Shao struct hclge_desc desc;
561939ccd10SJijie Shao u32 total_num;
562939ccd10SJijie Shao int ret;
563939ccd10SJijie Shao
564939ccd10SJijie Shao hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
565939ccd10SJijie Shao ret = hclge_cmd_send(&hdev->hw, &desc, 1);
566939ccd10SJijie Shao if (ret) {
567939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
568939ccd10SJijie Shao "Query register number cmd failed, ret = %d.\n", ret);
569939ccd10SJijie Shao return ret;
570939ccd10SJijie Shao }
571939ccd10SJijie Shao
572939ccd10SJijie Shao *regs_num_32_bit = le32_to_cpu(desc.data[0]);
573939ccd10SJijie Shao *regs_num_64_bit = le32_to_cpu(desc.data[1]);
574939ccd10SJijie Shao
575939ccd10SJijie Shao total_num = *regs_num_32_bit + *regs_num_64_bit;
576939ccd10SJijie Shao if (!total_num)
577939ccd10SJijie Shao return -EINVAL;
578939ccd10SJijie Shao
579939ccd10SJijie Shao return 0;
580939ccd10SJijie Shao }
581939ccd10SJijie Shao
hclge_get_regs_len(struct hnae3_handle * handle)582939ccd10SJijie Shao int hclge_get_regs_len(struct hnae3_handle *handle)
583939ccd10SJijie Shao {
584939ccd10SJijie Shao struct hnae3_knic_private_info *kinfo = &handle->kinfo;
585939ccd10SJijie Shao struct hclge_vport *vport = hclge_get_vport(handle);
586939ccd10SJijie Shao int regs_num_32_bit, regs_num_64_bit, dfx_regs_len;
587d8634b7cSJijie Shao int cmdq_len, common_len, ring_len, tqp_intr_len;
588d8634b7cSJijie Shao int regs_len_32_bit, regs_len_64_bit;
589d8634b7cSJijie Shao struct hclge_dev *hdev = vport->back;
590939ccd10SJijie Shao int ret;
591939ccd10SJijie Shao
592939ccd10SJijie Shao ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit);
593939ccd10SJijie Shao if (ret) {
594939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
595939ccd10SJijie Shao "Get register number failed, ret = %d.\n", ret);
596939ccd10SJijie Shao return ret;
597939ccd10SJijie Shao }
598939ccd10SJijie Shao
599939ccd10SJijie Shao ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len);
600939ccd10SJijie Shao if (ret) {
601939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
602939ccd10SJijie Shao "Get dfx reg len failed, ret = %d.\n", ret);
603939ccd10SJijie Shao return ret;
604939ccd10SJijie Shao }
605939ccd10SJijie Shao
606d8634b7cSJijie Shao cmdq_len = HCLGE_REG_TLV_SIZE + sizeof(cmdq_reg_addr_list);
607d8634b7cSJijie Shao common_len = HCLGE_REG_TLV_SIZE + sizeof(common_reg_addr_list);
608d8634b7cSJijie Shao ring_len = HCLGE_REG_TLV_SIZE + sizeof(ring_reg_addr_list);
609d8634b7cSJijie Shao tqp_intr_len = HCLGE_REG_TLV_SIZE + sizeof(tqp_intr_reg_addr_list);
610d8634b7cSJijie Shao regs_len_32_bit = HCLGE_REG_TLV_SIZE + regs_num_32_bit * sizeof(u32);
611d8634b7cSJijie Shao regs_len_64_bit = HCLGE_REG_TLV_SIZE + regs_num_64_bit * sizeof(u64);
612939ccd10SJijie Shao
613d8634b7cSJijie Shao /* return the total length of all register values */
614d8634b7cSJijie Shao return HCLGE_REG_HEADER_SIZE + cmdq_len + common_len + ring_len *
615d8634b7cSJijie Shao kinfo->num_tqps + tqp_intr_len * (hdev->num_msi_used - 1) +
616d8634b7cSJijie Shao regs_len_32_bit + regs_len_64_bit + dfx_regs_len;
617939ccd10SJijie Shao }
618939ccd10SJijie Shao
hclge_get_regs(struct hnae3_handle * handle,u32 * version,void * data)619939ccd10SJijie Shao void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
620939ccd10SJijie Shao void *data)
621939ccd10SJijie Shao {
622939ccd10SJijie Shao #define HCLGE_REG_64_BIT_SPACE_MULTIPLE 2
623939ccd10SJijie Shao
624939ccd10SJijie Shao struct hnae3_knic_private_info *kinfo = &handle->kinfo;
625939ccd10SJijie Shao struct hclge_vport *vport = hclge_get_vport(handle);
626939ccd10SJijie Shao struct hclge_dev *hdev = vport->back;
627939ccd10SJijie Shao u32 regs_num_32_bit, regs_num_64_bit;
628939ccd10SJijie Shao u32 *reg = data;
629d8634b7cSJijie Shao int ret;
630939ccd10SJijie Shao
631939ccd10SJijie Shao *version = hdev->fw_version;
632939ccd10SJijie Shao
633939ccd10SJijie Shao ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit);
634939ccd10SJijie Shao if (ret) {
635939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
636939ccd10SJijie Shao "Get register number failed, ret = %d.\n", ret);
637939ccd10SJijie Shao return;
638939ccd10SJijie Shao }
639939ccd10SJijie Shao
640d8634b7cSJijie Shao reg += hclge_reg_get_header(reg);
641939ccd10SJijie Shao reg += hclge_fetch_pf_reg(hdev, reg, kinfo);
642939ccd10SJijie Shao
643d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_QUERY_32_BIT,
644d8634b7cSJijie Shao regs_num_32_bit, reg);
645939ccd10SJijie Shao ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
646939ccd10SJijie Shao if (ret) {
647939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
648939ccd10SJijie Shao "Get 32 bit register failed, ret = %d.\n", ret);
649939ccd10SJijie Shao return;
650939ccd10SJijie Shao }
651d8634b7cSJijie Shao reg += regs_num_32_bit;
652939ccd10SJijie Shao
653d8634b7cSJijie Shao reg += hclge_reg_get_tlv(HCLGE_REG_TAG_QUERY_64_BIT,
654d8634b7cSJijie Shao regs_num_64_bit *
655d8634b7cSJijie Shao HCLGE_REG_64_BIT_SPACE_MULTIPLE, reg);
656939ccd10SJijie Shao ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
657939ccd10SJijie Shao if (ret) {
658939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
659939ccd10SJijie Shao "Get 64 bit register failed, ret = %d.\n", ret);
660939ccd10SJijie Shao return;
661939ccd10SJijie Shao }
662d8634b7cSJijie Shao reg += regs_num_64_bit * HCLGE_REG_64_BIT_SPACE_MULTIPLE;
663939ccd10SJijie Shao
664939ccd10SJijie Shao ret = hclge_get_dfx_reg(hdev, reg);
665939ccd10SJijie Shao if (ret)
666939ccd10SJijie Shao dev_err(&hdev->pdev->dev,
667939ccd10SJijie Shao "Get dfx register failed, ret = %d.\n", ret);
668939ccd10SJijie Shao }
669