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Searched refs:ddrphy (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c225 fdt_addr_t ddrphy; member
299 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); in mtk_ddr3_init()
300 writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2); in mtk_ddr3_init()
302 writel(0x10, priv->ddrphy + DDRPHY_PLL3); in mtk_ddr3_init()
335 writel(0x0, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()
336 writel(0x0, priv->ddrphy + DDRPHY_PLL2); in mtk_ddr3_init()
431 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7); in mtk_ddr3_init()
432 writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7); in mtk_ddr3_init()
435 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); in mtk_ddr3_init()
446 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8); in mtk_ddr3_init()
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A DMakefile6 ddrphy-training.o ddrphy-ld4.o
8 ddrphy-training.o ddrphy-ld4.o
10 ddrphy-training.o ddrphy-ld4.o
/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c358 setbits_le32(&ddrphy->reg[0], BIT(2)); in ddrphy_reset()
360 setbits_le32(&ddrphy->reg[0], BIT(3)); in ddrphy_reset()
367 setbits_le32(&ddrphy->reg[0x13], BIT(4)); in ddrphy_config_delays()
383 setbits_le32(&ddrphy->reg[0xa4], 0x1f); in ddrphy_config_delays()
385 clrbits_le32(&ddrphy->reg[0xa4], 0x1f); in ddrphy_config_delays()
570 struct rk3368_ddrphy *ddrphy) in ddrphy_data_training() argument
818 ddrphy_reset(ddrphy); in setup_sdram()
829 ddrphy_config(ddrphy, in setup_sdram()
841 ddrphy_data_training(pctl, ddrphy); in setup_sdram()
907 struct rk3368_ddrphy *ddrphy; in rk3368_dmc_probe() local
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A DKconfig109 The command "ddrphy" shows the resulting parameters of DDR PHY
/openbmc/u-boot/doc/
H A DREADME.uniphier396 - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)