| /openbmc/u-boot/board/atmel/sama5d27_som1_ek/ |
| H A D | sama5d27_som1_ek.c | 101 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
103 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddrc_conf()
105 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
114 ddrc->rtr = 0x511; in ddrc_conf()
116 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
125 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
130 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
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| /openbmc/u-boot/board/atmel/sama5d2_xplained/ |
| H A D | sama5d2_xplained.c | 102 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
104 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
106 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
115 ddrc->rtr = 0x511; in ddrc_conf()
117 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
126 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
131 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
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| /openbmc/linux/drivers/power/reset/ |
| H A D | at91-sama5d2_shdwc.c | 89 struct ddrc_reg_config ddrc; member
271 .ddrc = {
288 .ddrc = {
386 if (at91_shdwc->rcfg->ddrc.type_mask) { in at91_shdwc_probe()
403 at91_shdwc->rcfg->ddrc.type_offset) & in at91_shdwc_probe()
404 at91_shdwc->rcfg->ddrc.type_mask; in at91_shdwc_probe()
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| /openbmc/u-boot/arch/arm/mach-imx/mx7/ |
| H A D | ddr.c | 27 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, in mx7_dram_cfg()
32 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in mx7_dram_cfg()
113 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in imx_ddr_size()
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx7/ |
| H A D | mx7-ddr.h | 14 struct ddrc { struct
150 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
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| /openbmc/u-boot/arch/arm/mach-zynq/ |
| H A D | Makefile | 11 obj-y += ddrc.o
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| /openbmc/u-boot/board/hisilicon/hikey/ |
| H A D | README | 125 INFO: succeed to set ddrc 150mhz
127 INFO: succeed to set ddrc 266mhz
129 INFO: succeed to set ddrc 400mhz
131 INFO: succeed to set ddrc 533mhz
133 INFO: succeed to set ddrc 800mhz
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| /openbmc/linux/drivers/devfreq/ |
| H A D | Makefile | 13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
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| /openbmc/u-boot/board/technexion/pico-imx7d/ |
| H A D | spl.c | 24 static struct ddrc ddrc_regs_val = {
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| /openbmc/linux/arch/mips/include/asm/mach-rc32434/ |
| H A D | ddr.h | 40 u32 ddrc; member
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| /openbmc/u-boot/board/compulab/cl-som-imx7/ |
| H A D | spl.c | 37 static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mm-evk.dts | 20 &ddrc {
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| H A D | imx8mn-ddr4-evk.dts | 32 &ddrc {
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| H A D | imx8mm-kontron-sl.dtsi | 43 &ddrc {
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| H A D | imx8mm-kontron-osm-s.dtsi | 49 &ddrc {
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| H A D | imx8mq.dtsi | 1570 fsl,ddrc = <&ddrc>;
1858 ddrc: memory-controller@3d400000 { label
1859 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
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| H A D | imx8mm-phycore-som.dtsi | 50 &ddrc {
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| H A D | imx8mm-venice-gw700x.dtsi | 78 &ddrc {
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| H A D | imx8mm-beacon-som.dtsi | 44 &ddrc {
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| H A D | imx8mn-beacon-som.dtsi | 52 &ddrc {
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| H A D | imx8mm-innocomm-wb15.dtsi | 38 &ddrc {
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ctrl_regs.c | 2370 struct ccsr_ddr __iomem *ddrc; in compute_fsl_memctl_config_regs() local
2374 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; in compute_fsl_memctl_config_regs()
2378 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in compute_fsl_memctl_config_regs()
2383 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in compute_fsl_memctl_config_regs()
2388 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in compute_fsl_memctl_config_regs()
2623 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2631 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
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| /openbmc/linux/arch/arm64/boot/dts/intel/ |
| H A D | socfpga_n5x_socdk.dts | 30 compatible = "snps,ddrc-3.80a";
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | hisi-pmu.rst | 23 /sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
24 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-7000.dtsi | 158 compatible = "xlnx,zynq-ddrc-a05";
|