| /openbmc/u-boot/board/atmel/sama5d27_som1_ek/ |
| H A D | sama5d27_som1_ek.c | 101 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
103 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddrc_conf()
105 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
114 ddrc->rtr = 0x511; in ddrc_conf()
116 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
125 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
130 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
|
| /openbmc/u-boot/board/atmel/sama5d2_xplained/ |
| H A D | sama5d2_xplained.c | 102 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
104 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
106 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
115 ddrc->rtr = 0x511; in ddrc_conf()
117 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
126 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
131 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
|
| /openbmc/u-boot/arch/arm/mach-imx/mx7/ |
| H A D | ddr.c | 27 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, in mx7_dram_cfg()
32 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in mx7_dram_cfg()
113 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in imx_ddr_size()
|
| /openbmc/u-boot/arch/arm/include/asm/arch-mx7/ |
| H A D | mx7-ddr.h | 14 struct ddrc { struct
150 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
|
| /openbmc/u-boot/arch/arm/mach-zynq/ |
| H A D | Makefile | 11 obj-y += ddrc.o
|
| /openbmc/u-boot/board/technexion/pico-imx7d/ |
| H A D | spl.c | 24 static struct ddrc ddrc_regs_val = {
|
| /openbmc/u-boot/board/hisilicon/hikey/ |
| H A D | README | 125 INFO: succeed to set ddrc 150mhz
127 INFO: succeed to set ddrc 266mhz
129 INFO: succeed to set ddrc 400mhz
131 INFO: succeed to set ddrc 533mhz
133 INFO: succeed to set ddrc 800mhz
|
| /openbmc/u-boot/board/compulab/cl-som-imx7/ |
| H A D | spl.c | 37 static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
|
| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ctrl_regs.c | 2370 struct ccsr_ddr __iomem *ddrc; in compute_fsl_memctl_config_regs() local
2374 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; in compute_fsl_memctl_config_regs()
2378 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in compute_fsl_memctl_config_regs()
2383 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in compute_fsl_memctl_config_regs()
2388 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in compute_fsl_memctl_config_regs()
2623 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2631 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-7000.dtsi | 158 compatible = "xlnx,zynq-ddrc-a05";
|
| H A D | tegra20-tamonten.dtsi | 183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
| H A D | tegra20-paz00.dts | 227 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
| H A D | tegra20-ventana.dts | 245 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
| H A D | tegra20-harmony.dts | 233 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
| H A D | tegra20-seaboard.dts | 255 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
| H A D | zynqmp.dtsi | 488 compatible = "xlnx,zynqmp-ddrc-2.40a";
|
| /openbmc/ |
| D | opengrok1.0.log | [all...] |
| D | opengrok2.0.log | [all...] |