| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_init.c | 9 static char *ddr_type = "DDR3"; variable
37 mv_ddr_pre_training_soc_config(ddr_type); in ddr3_init()
76 printf("%s Training Sequence - FAILED\n", ddr_type); in ddr3_init()
85 mv_ddr_post_training_soc_config(ddr_type); in ddr3_init()
136 printf("%s Training Sequence - FAILED\n", ddr_type); in mv_ddr_training_params_set()
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| H A D | mv_ddr_plat.h | 225 int mv_ddr_pre_training_soc_config(const char *ddr_type);
226 int mv_ddr_post_training_soc_config(const char *ddr_type);
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| H A D | mv_ddr_plat.c | 1104 static int ddr3_restore_and_set_final_windows(u32 *win, const char *ddr_type) in ddr3_restore_and_set_final_windows() argument
1118 ddr_type); in ddr3_restore_and_set_final_windows()
1212 int mv_ddr_pre_training_soc_config(const char *ddr_type) in mv_ddr_pre_training_soc_config() argument
1249 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); in mv_ddr_pre_training_soc_config()
1322 int mv_ddr_post_training_soc_config(const char *ddr_type) in mv_ddr_post_training_soc_config() argument
1327 ddr3_restore_and_set_final_windows(win, ddr_type); in mv_ddr_post_training_soc_config()
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| /openbmc/u-boot/board/rockchip/evb_rk3036/ |
| H A D | evb_rk3036.c | 15 config->ddr_type = 3; in get_ddr_config()
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| /openbmc/u-boot/board/rockchip/kylin_rk3036/ |
| H A D | kylin_rk3036.c | 16 config->ddr_type = 3; in get_ddr_config()
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| /openbmc/u-boot/board/ccv/xpress/ |
| H A D | spl.c | 61 .ddr_type = DDR_TYPE_DDR3,
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| /openbmc/u-boot/board/barco/platinum/ |
| H A D | spl_picon.c | 137 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| H A D | spl_titanium.c | 140 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | global_data.h | 23 uint16_t ddr_type; member
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| /openbmc/u-boot/drivers/ram/ |
| H A D | mpc83xx_sdram.c | 317 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; in mpc83xx_sdram_probe() local
409 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); in mpc83xx_sdram_probe()
410 if (ddr_type > 1) { in mpc83xx_sdram_probe()
412 dev->name, ddr_type); in mpc83xx_sdram_probe()
434 ddr_type << (31 - 13) | in mpc83xx_sdram_probe()
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| /openbmc/u-boot/arch/x86/include/asm/arch-quark/ |
| H A D | mrc.h | 114 uint8_t ddr_type; /* DDR3, DDR3L */ member
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| /openbmc/u-boot/board/phytec/pcl063/ |
| H A D | spl.c | 66 .ddr_type = DDR_TYPE_DDR3,
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| /openbmc/u-boot/board/engicam/common/ |
| H A D | spl.c | 233 .ddr_type = DDR_TYPE_DDR3,
345 .ddr_type = DDR_TYPE_DDR3,
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | litesom.c | 129 .ddr_type = DDR_TYPE_DDR3,
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| H A D | opos6ul.c | 194 .ddr_type = DDR_TYPE_DDR3,
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| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | spl.c | 232 .ddr_type = DDR_TYPE_DDR3,
237 .ddr_type = DDR_TYPE_LPDDR2,
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | dram.c | 81 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); in mrc_configure_params()
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| /openbmc/u-boot/board/liebherr/display5/ |
| H A D | spl.c | 182 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| /openbmc/u-boot/Documentation/devicetree/bindings/ram/ |
| H A D | fsl,mpc83xx-mem-controller.txt | 36 - ddr_type: Selects voltage level for DDR pads; possible
258 ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
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| /openbmc/u-boot/board/freescale/mx6ul_14x14_evk/ |
| H A D | mx6ul_14x14_evk.c | 638 .ddr_type = DDR_TYPE_LPDDR2,
678 .ddr_type = DDR_TYPE_DDR3,
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| /openbmc/u-boot/board/k+p/kp_imx6q_tpc/ |
| H A D | kp_imx6q_tpc_spl.c | 245 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| /openbmc/u-boot/board/freescale/mx6slevk/ |
| H A D | mx6slevk.c | 413 .ddr_type = DDR_TYPE_LPDDR2, in spl_dram_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3036.h | 319 u32 ddr_type; member
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| /openbmc/u-boot/board/phytec/pcm058/ |
| H A D | pcm058.c | 507 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| /openbmc/u-boot/board/gateworks/gw_ventana/ |
| H A D | gw_ventana_spl.c | 509 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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