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Searched refs:dbw (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3399.h83 unsigned int dbw; member
H A Dsdram.h27 u8 dbw; member
H A Dsdram_rk322x.h27 u8 dbw; member
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk322x.c593 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0); in dram_all_config()
608 sdram_params->ch[0].dbw = 1; in dram_cap_detect()
610 sdram_params->ch[0].dbw = 2; in dram_cap_detect()
H A Ddmc-rk3368.c788 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); in dram_all_config()
848 params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ in setup_sdram()
H A Dsdram_rk3188.c552 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); in dram_all_config()
600 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
H A Dsdram_rk3288.c609 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); in dram_all_config()
653 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
H A Dsdram_rk3399.c959 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); in dram_all_config()
/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c792 unsigned int dbw; /* DRAM dta bus width */ in set_ddr_sdram_cfg() local
826 dbw = popts->data_bus_width; in set_ddr_sdram_cfg()
837 if (dbw == 0x1) in set_ddr_sdram_cfg()
846 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; in set_ddr_sdram_cfg()
855 | ((dbw & 0x3) << 19) in set_ddr_sdram_cfg()
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt99 dbw