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Searched refs:ctrl_reg (Results 1 – 25 of 100) sorted by relevance

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/openbmc/u-boot/drivers/mmc/
H A Dmvebu_mmc.c40 u32 ctrl_reg; in mvebu_mmc_setup_data() local
47 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); in mvebu_mmc_setup_data()
48 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); in mvebu_mmc_setup_data()
49 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); in mvebu_mmc_setup_data()
281 u32 ctrl_reg = 0; in mvebu_mmc_set_bus() local
283 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); in mvebu_mmc_set_bus()
284 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; in mvebu_mmc_set_bus()
288 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; in mvebu_mmc_set_bus()
292 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; in mvebu_mmc_set_bus()
296 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN; in mvebu_mmc_set_bus()
[all …]
/openbmc/linux/drivers/watchdog/
H A Dmachzwd.c188 unsigned int ctrl_reg = 0; in zf_timer_off() local
196 ctrl_reg = zf_get_control(); in zf_timer_off()
197 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */ in zf_timer_off()
198 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2); in zf_timer_off()
199 zf_set_control(ctrl_reg); in zf_timer_off()
211 unsigned int ctrl_reg = 0; in zf_timer_on() local
227 ctrl_reg = zf_get_control(); in zf_timer_on()
228 ctrl_reg |= (ENABLE_WD1|zf_action); in zf_timer_on()
229 zf_set_control(ctrl_reg); in zf_timer_on()
238 unsigned int ctrl_reg = 0; in zf_ping() local
[all …]
/openbmc/linux/drivers/clk/microchip/
H A Dclk-core.c91 void __iomem *ctrl_reg; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
185 v = readl(pb->ctrl_reg); in pbclk_set_rate()
191 writel(v, pb->ctrl_reg); in pbclk_set_rate()
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
226 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-cadence.c155 u32 ctrl_reg = 0; in cdns_spi_init_hw() local
158 ctrl_reg |= CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw()
161 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
171 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
183 u32 ctrl_reg; in cdns_spi_chipselect() local
185 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); in cdns_spi_chipselect()
189 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
192 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
194 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) << in cdns_spi_chipselect()
198 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) & in cdns_spi_chipselect()
[all …]
H A Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
61 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
102 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
120 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
124 writel(xmit, ctrl_reg); in jcore_spi_txrx()
126 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
/openbmc/linux/drivers/bluetooth/
H A Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
307 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
308 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
309 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
312 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
313 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
513 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_interrupt()
[all …]
/openbmc/linux/drivers/ntb/hw/epf/
H A Dntb_hw_epf.c75 void __iomem *ctrl_reg; member
108 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT); in ntb_epf_send_command()
109 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND); in ntb_epf_send_command()
114 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
132 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
200 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS); in ntb_epf_link_is_up()
216 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_read()
219 return readl(ndev->ctrl_reg + offset); in ntb_epf_spad_read()
234 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_write()
236 writel(val, ndev->ctrl_reg + offset); in ntb_epf_spad_write()
[all …]
/openbmc/linux/drivers/pci/hotplug/
H A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
[all …]
H A Dshpchp.h177 struct ctrl_reg { struct
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), argument
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
199 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
201 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
[all …]
/openbmc/linux/drivers/net/wireless/st/cw1200/
H A Dbh.c173 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg() argument
178 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
181 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
191 u16 ctrl_reg; in cw1200_device_wakeup() local
208 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg); in cw1200_device_wakeup()
215 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
233 uint16_t *ctrl_reg, in cw1200_bh_rx_helper() argument
247 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2; in cw1200_bh_rx_helper()
254 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
288 *ctrl_reg = __le16_to_cpu( in cw1200_bh_rx_helper()
[all …]
/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all …]
/openbmc/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c66 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, in phy_berlin_sata_reg_setbits() argument
72 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
75 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
78 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on() local
105 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
110 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
114 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
118 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
122 regval = readl(ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
[all …]
/openbmc/linux/drivers/misc/ibmasm/
H A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/
H A D0001-remoteproc-Add-Arm-remoteproc-driver.patch112 + * @ctrl_reg: address of the control register
116 + void __iomem *ctrl_reg;
175 + u32 ctrl_reg;
178 + ctrl_reg = readl(priv->reset_cfg.ctrl_reg);
179 + ctrl_reg &= ~EXTSYS_RST_CTRL_CPUWAIT;
180 + writel(ctrl_reg, priv->reset_cfg.ctrl_reg);
249 + u32 ctrl_reg;
253 + ctrl_reg = readl(priv->reset_cfg.ctrl_reg);
254 + ctrl_reg |= EXTSYS_RST_CTRL_RST_REQ;
255 + writel(ctrl_reg, priv->reset_cfg.ctrl_reg);
[all …]
/openbmc/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c113 u32 ctrl_reg; in ttc_set_interval() local
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
117 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
126 ctrl_reg |= CNT_CNTRL_RESET; in ttc_set_interval()
127 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
197 u32 ctrl_reg; in ttc_shutdown() local
199 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
200 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_shutdown()
[all …]
/openbmc/linux/drivers/net/wireless/silabs/wfx/
H A Dbh.c137 int ctrl_reg, piggyback; in bh_work_rx() local
142 ctrl_reg = piggyback; in bh_work_rx()
144 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
146 ctrl_reg = 0; in bh_work_rx()
147 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
150 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
159 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggyback); in bh_work_rx()
161 if (ctrl_reg) in bh_work_rx()
163 ctrl_reg, piggyback); in bh_work_rx()
268 prev = atomic_xchg(&wdev->hif.ctrl_reg, cur); in wfx_bh_request_rx()
/openbmc/u-boot/drivers/power/regulator/
H A Dpalmas_regulator.c57 adr = uc_pdata->ctrl_reg; in palmas_smps_enable()
181 adr = p->ctrl_reg; in palmas_ldo_bypass_enable()
202 adr = uc_pdata->ctrl_reg; in palmas_ldo_enable()
307 uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx]; in palmas_ldo_probe()
312 uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9]; in palmas_ldo_probe()
315 uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10]; in palmas_ldo_probe()
376 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][0]; in palmas_smps_probe()
380 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][1]; in palmas_smps_probe()
384 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][2]; in palmas_smps_probe()
393 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx]; in palmas_smps_probe()
[all …]
H A Das3722_regulator.c73 u8 ctrl_reg = AS3722_LDO_CONTROL0; in ldo_set_enable() local
78 ctrl_reg = AS3722_LDO_CONTROL1; in ldo_set_enable()
82 ret = pmic_clrsetbits(pmic, ctrl_reg, !enable << ldo, enable << ldo); in ldo_set_enable()
95 u8 ctrl_reg = AS3722_LDO_CONTROL0; in ldo_get_enable() local
100 ctrl_reg = AS3722_LDO_CONTROL1; in ldo_get_enable()
104 ret = pmic_reg_read(pmic, ctrl_reg); in ldo_get_enable()
/openbmc/linux/drivers/tty/serial/
H A Dxilinx_uartps.c482 u32 ctrl_reg; in cdns_uart_clk_notifier_cb() local
512 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
513 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; in cdns_uart_clk_notifier_cb()
514 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
539 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
540 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; in cdns_uart_clk_notifier_cb()
541 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
553 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
554 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); in cdns_uart_clk_notifier_cb()
555 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; in cdns_uart_clk_notifier_cb()
[all …]
/openbmc/linux/drivers/fpga/
H A Dsocfpga.c337 u32 ctrl_reg; in socfpga_fpga_cfg_mode_set() local
346 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_cfg_mode_set()
347 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; in socfpga_fpga_cfg_mode_set()
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; in socfpga_fpga_cfg_mode_set()
349 ctrl_reg |= cfgmgr_modes[mode].ctrl; in socfpga_fpga_cfg_mode_set()
352 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; in socfpga_fpga_cfg_mode_set()
353 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); in socfpga_fpga_cfg_mode_set()
361 u32 ctrl_reg, status; in socfpga_fpga_reset() local
378 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_reset()
379 ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; in socfpga_fpga_reset()
[all …]
/openbmc/linux/drivers/input/rmi4/
H A Drmi_f30.c275 u8 *ctrl_reg = f30->ctrl_regs; in rmi_f30_initialize() local
300 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
303 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
307 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
310 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
315 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
319 &ctrl_reg); in rmi_f30_initialize()
325 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
331 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
336 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-cadence.c212 u32 ctrl_reg; member
570 unsigned int ctrl_reg; in cdns_i2c_mrecv() local
582 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
583 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_mrecv()
600 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_mrecv()
602 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
624 if (ctrl_reg & CDNS_I2C_CR_HOLD) { in cdns_i2c_mrecv()
635 ctrl_reg &= ~CDNS_I2C_CR_HOLD; in cdns_i2c_mrecv()
636 ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_mrecv()
648 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dmxc_spi.c44 u32 ctrl_reg; member
94 unsigned int ctrl_reg; in spi_cfg_mxc() local
108 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | in spi_cfg_mxc()
118 ctrl_reg |= MXC_CSPICTRL_PHA; in spi_cfg_mxc()
120 ctrl_reg |= MXC_CSPICTRL_POL; in spi_cfg_mxc()
122 ctrl_reg |= MXC_CSPICTRL_SSPOL; in spi_cfg_mxc()
123 mxcs->ctrl_reg = ctrl_reg; in spi_cfg_mxc()
207 mxcs->ctrl_reg = reg_ctrl; in spi_cfg_mxc()
230 mxcs->ctrl_reg = (mxcs->ctrl_reg & in spi_xchg_single()
234 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); in spi_xchg_single()
[all …]
/openbmc/linux/drivers/regulator/
H A Dvctrl-regulator.c323 struct regulator *ctrl_reg) in vctrl_init_vtable() argument
332 n_voltages = regulator_count_voltages(ctrl_reg); in vctrl_init_vtable()
338 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
358 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
450 struct regulator *ctrl_reg; in vctrl_probe() local
465 ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl"); in vctrl_probe()
466 if (IS_ERR(ctrl_reg)) in vctrl_probe()
467 return PTR_ERR(ctrl_reg); in vctrl_probe()
477 if ((regulator_get_linear_step(ctrl_reg) == 1) || in vctrl_probe()
478 (regulator_count_voltages(ctrl_reg) == -EINVAL)) { in vctrl_probe()
[all …]
/openbmc/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h391 u32 ctrl_reg; in disable_raw_feature() local
393 ctrl_reg = VPIF_CH0_CTRL; in disable_raw_feature()
395 ctrl_reg = VPIF_CH1_CTRL; in disable_raw_feature()
398 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in disable_raw_feature()
400 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in disable_raw_feature()
405 u32 ctrl_reg; in enable_raw_feature() local
407 ctrl_reg = VPIF_CH0_CTRL; in enable_raw_feature()
409 ctrl_reg = VPIF_CH1_CTRL; in enable_raw_feature()
412 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in enable_raw_feature()
414 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in enable_raw_feature()

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